News Highlights
NPS is a new product line of NPUs that uniquely features a combination of unmatched:
- Technology - 10 times smaller and faster C-programmable Task Optimized Processors (CTOPs)
- Integration - NPU with 256 CTOPs, 4K threads, Traffic Manager, DPI, Security, Search Engine and 800G I/O in one chip
- Performance - 400-Gigabit wire-speed packet processing
- Flexibility - advanced services and full layers 2-7 stateful processing
- Simplicity - easy to use C-programmable and Linux® operating system
- Versatility - addressing carrier, cloud and data-center networking equipment
- Applications - switching, routing, SDN/OpenFlow and virtualization of network elements, load balancing, TCP offload, firewall, VPNs, intrusion detection/prevention, network analytics and more
EZchip Semiconductor Ltd. (NASDAQ: EZCH), a leader in Ethernet network processors, today unveiled the NPS - Network Processor for Smart networks - a revolutionary network processor (NPU) that will enable the next generation of smart high-performance carrier and data-center equipment. Through its breakthrough architecture the NPS boosts the flexibility and performance of traditional NPUs and CPUs to enable advanced baseline features for carrier equipment and to scale the performance levels of data-center equipment. NPS provides equipment vendors with a feature-proof, fully programmable, high performance solution and expands the market addressable by EZchip's NPUs. EZchip will present details of the NPS architecture at the Linley Tech Processor Conference on October 10-11, 2012 in San Jose, California.
With the continuous surge of subscribers, content and applications on the net, carrier and data-center networks are under constant pressure to operate faster and do more. This demand for network bandwidth and intelligence produces an insatiable appetite for processing power in networking equipment. Network-equipment vendors essentially have had a choice of two types of processors: NPUs that provide fast layer 2-3 processing however with complex microcode programming, and CPUs (single or multi-core) that provide flexible C-programmable layer 4-7 processing however at reduced performance and power efficiency. Through its breakthrough architecture, NPS breaks the barriers imposed by traditional NPUs and CPUs. It enables extremely high-performance C-programmable layer 2-7 processing, and provides networking vendors with an architecture that scales as more advanced services at higher speeds are required over time.
For carrier equipment, the NPS enables the migration of advanced layer 4-7 features from specialized services cards to common line cards and enables the line card with new baseline features such as application recognition and IPSec VPNs, as well as greater velocity for adding new features. For data-center equipment, the NPS allows scaling their performance to the required loads of the evolving data center for greater layer 2-7 capabilities within constrained power and space. It empowers data-center appliances as well as carrier appliances with line-rate performance for applications such as load balancing, firewall and OpenFlow/SDN (Software Defined Networks) and network virtualization.
The NPS is uniquely designed for data-plane processing where packet processing and wire-speed forwarding prevail, unlike CPUs that are designed for general processing where management functions and control-plane processing prevail. Central to the NPS are its innovative CTOPs (C-programmable Task Optimized Processors). These processing engines build on EZchip's extensive NPU experience and are designed specifically for data-plane processing. The optimized design allows the integration of 256 such processors, each with 16 threads, for a total of 4K virtual processing engines. This vast number of engines is mandatory for high-speed data-plane processing where packets are arriving at an extremely high rate and every packet is processed. The NPS architecture is in contrast to CPUs that have an order of magnitude fewer engines integrated into a chip because they are based on much larger general-purpose cores, have large memory caches, designed to execute millions lines of code, and target both data and control processing. The NPS' efficient design allows incorporating into the chip not only a great number of cores but also EZchip's market-proven hardware traffic manager, a task optimized memory architecture, and numerous hardware accelerators for efficient table lookups, application recognition and security. The end result is a very powerful network processor with superior power efficiency and integration.
"We are bringing to market a new breed of network processor that is architected to address the next generation of smart high-performance carrier and data-center networks. Leveraging the 10-years of experience with our NP family that made EZchip the leading high-speed NPU supplier, we believe the NPS will extend and broaden our leadership for many years to come. We are preserving NPU performance advantages, opening the L4-7 markets for us and doubling EZchip's addressable market above and beyond serving edge routers," said Eli Fruchter, President and CEO of EZchip Technologies. "As for our main market of edge routers, NPS extends our competitive advantage and leapfrogs the competition. Combined with our future NP products, NPS can potentially increase our market penetration in next generation edge routing by providing current and new customers with the flexibility to adopt existing or new architectures, for basic and advanced line cards."
"We applaud EZchip for its bold move in developing the NPS, which truly redefines the network processor by stripping away traditional limitations," said Bob Wheeler, senior analyst at The Linley Group. "Only the market leader could develop such a ground-breaking product as the NPS while preserving its customers' software investments by also extending the NP line."
The NPS is a new product line of NPUs from EZchip. Initially, EZchip will deliver the NPS-400 and NPS-200 products with 400-Gigabit and 200-Gigabit throughput, respectively. Samples are planned for Q4 2013 and other derivative products will follow. EZchip customers for the NP-2/3/4/5 products will have the option to maintain the benefits of code portability and scale up with a future NP-6, or C-program their applications and benefit from the new capabilities of the NPS.
The NPS provides great packet processing simplicity and flexibility through C-based programming, a standard toolset, support of the Linux® operating system, large code space, and a run-to-completion or pipeline programming style. A comprehensive library provides source code for a variety of applications to speed customer's design cycle. The NPS features cores that are highly optimized for packet processing and leverage EZchip's vast packet processing and applications experience, a market-proven traffic manager, hardware accelerators for security and DPI (Deep Packet Inspection) tailored for efficiency and performance, on-chip search engines including TCAM with scaling through algorithmic extension to external low-cost low-power DRAM memory, a fabric adaptor to enable direct connection to a chassis backplane and switch fabric, and a multitude of interfaces providing an aggregated bandwidth of 800-Gigabits per second including 10-, 40- and 100-Gigabit Ethernet, Interlaken and PCI Express interfaces.
Webcast Discusses New Product Line
EZchip will be hosting and webcasting a conference call with analysts and investors on September 5, 2012 at 10:00am Eastern Time (7:00am Pacific Time; 5:00pm Israel Time). The accompanying presentation is now available on the company's website. The live webcast and presentation are available from a link in the investor relations section of the Company's web site at: http://www.ezchip.com/investor_relations.htm. An archived webcast replay will be available for a limited period.
About EZchip
EZchip is a fabless semiconductor company that provides Ethernet network processors for networking equipment. EZchip provides solutions that scale from a few to hundreds of Gigabits-per-second. EZchip's network processors provide great flexibility and high performance coupled with superior integration and power efficiency for a wide range of applications in carrier, cloud and data center network equipment. For more information on our company, visit the web site at http://www.ezchip.com.
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Forward-looking statements are statements that are not historical facts and may include financial projections and estimates and their underlying assumptions, statements regarding plans, objectives and expectations with respect to future operations, products and services, and statements regarding future performance. These statements are only predictions based on EZchip's current expectations and projections about future events. There are important factors that could cause EZchip's actual results, level of activity, performance or achievements to differ materially from the results, level of activity, performance or achievements expressed or implied by the forward-looking statements. Those factors include, but are not limited to, the impact of general economic conditions, competitive products, product demand and market acceptance risks, customer order cancellations, reliance on key strategic alliances, fluctuations in operating results, delays in development of highly-complex products and other factors indicated in EZchip's filings with the Securities and Exchange Commission (SEC). For more details, refer to EZchip's SEC filings and the amendments thereto, including its Annual Report on Form 20-F filed on March 29, 2012 and its Current Reports on Form 6-K. EZchip undertakes no obligation to update forward-looking statements to reflect subsequent occurring events or circumstances, or to changes in our expectations, except as may be required by law.
