With the introduction of Intelli DDR3, Virage Logic extends its leadership in providing advanced technology solutions beyond the chip level to address the system-level impact on high-speed IP interfaces, such as DDR interfaces. Building on its Silicon Aware IP offering that addresses the impact of advanced process behavior on System-on-Chip (SoC) devices, the new Intelli DDR3 System Aware IP offering is capable of managing the impact of the environment – SoC core to interface, interface to package, package to board – on the system behavior and performance. System Aware IP is built for signal integrity awareness, yet meets the functional, as well as performance, power, and area requirements.
“As system level performance requirements continue to increase and market windows continue to shrink, a block by block approach is no longer viable to deliver competitive system solutions in the market window. In keeping with our mission to be first-to-market with advanced technology solutions that enable designers to proceed with confidence at the most aggressive DDR protocols, we have architected our Intelli DDR3 product to be completely system aware,” said Kamalesh Ruparel, vice president and general manager of Virage Logic’s application specific IP (ASIP) business. “Because Intelli DDR3 is able to address the system level impact of high-speed IP interfaces, it is capable of managing the impact of the environment on the system behavior and performance, spanning SoC core to interface, interface to package, and package to board. This end-to-end solution approach results in a higher performance solution at significantly lower risk and cost.”
About Intelli DDR3
Virage Logic’s Intelli DDR3 provides application specific integrated circuit (ASIC) and SoC designers with a high-performance, System Aware IP solution for faster time-to-market, higher data throughput efficiency, lower system costs, less power usage, and high confidence for first time silicon success. Intelli DDR3’s unique digital architecture and system intelligence helps manage the variables inherent in system designs, easing implementation and optimizing integration with existing board and package designs. The standard cell architecture and all-digital implementation enables the Intelli DDR3 solution to work seamlessly with digital SoC design flows, allowing significant ease of portability to any process node for any foundry, eliminating the need to prove the solution when integrated with silicon proven I/Os.
A versatile solution for lower power in a broad range of high-performance applications including networking, video, graphics, storage, test and measurement, and portable electronics, the innovative Intelli DDR3 solution utilizes Virage Logic’s unique patent-pending digital DLL architecture, enabling it to achieve the high resolution required to support data rates up to 1.6 Gb/s on 65nm G processes. The Intelli DDR3’s advanced architecture allows much higher data throughput efficiency than previously available architectures. Such high efficiencies enable designs to operate at lower frequencies, resulting in lower power consumption and bill of materials costs that translate to lower system costs.
Pricing and Availability
The Intelli DDR3 solution for the 65nm G process is available now for early adopters with pricing starting at $180,000 per project. Virage Logic also offers an optional system level design review service. Contact your local sales representative for pricing information.
About Virage Logic’s Silicon Aware IP and System Aware IP Solutions
To help SoC designers address the complex predictability and manufacturability challenges at advanced process nodes, in 2005 Virage Logic pioneered a new class of semiconductor IP called Silicon Aware IP. The company’s Silicon Aware IP offering (embedded memories, logic libraries and I/Os) incorporates silicon behavior knowledge for increased predictability and manufacturability. This intelligence includes hardware implementations for optimal yield in the design phase and extends to include test, repair, and diagnostics for manufacturability. Because Silicon Aware IP understands the behavior of silicon and is able to address post-silicon issues, it is key in helping designers maximize yield, increase test quality, increase reliability, speed time-to-volume, and improve overall manufacturability.
To help systems designers address the challenges of the environment –
SoC core to interface, interface to package, package to board, and other
SoCs – including the impact on the system
behavior and performance, Virage Logic introduced System Aware IP.
System Aware IP is designed to mitigate any impact the environment may
have on the overall system to ensure performance and functionality
requirements are met.
