"Accurate cell models characterized by precise circuit simulation are key to the silicon success of nanometer SoC designs," stated Dr. You-Pang Wei, president and CEO of Legend Design Technology. "Since the models reflect the reality of silicon, an integrated SIP optimization flow combining tool sets from Prolific, Circuit Semantics, and Legend provides a cost-effective solution for the ultra-competitive semiconductor market segments."
"As the industry moves to process technologies of 90 nanometer and below, semiconductor design flows require tools that consider yield and manufacturability," added Ewald Detjens, CEO of Circuit Semantics Inc. "For libraries optimized for manufacturability, accurate characterization and modeling is required to reflect the changes in timing, power consumption, and area. By working together, we offer accurate characterization and modeling as well as the optimized physical layouts required for high-yield nanometer processes."
"The design-to-manufacture chasm is growing at an alarming rate as chip size and complexity increase and process geometries decrease, and as market pressures increase and product life-cycles decrease," remarked Dan Nenni, vice president of sales and marketing at Prolific. "The emerging state of nanometer semiconductor production demands that designers take manufacturability into consideration up front, rather than leaving it as an expensive and time-consuming afterthought and standard cells, the building blocks of modern semiconductor design, is the natural starting point for this effort."
Prolific DFM SIP has addressed more than twenty manufacturing enhancement practices. These include decreasing the likelihood of contact/via failures by increasing contact/via metal overlap, using wider and longer metal end-of-line extensions, and using redundant vias/contacts. The number of critical features can be reduced by limiting poly and diffusion routing, using straight transistors, minimizing the number of vertices, and avoiding forbidden pitches. Optical & Process correction (OPC) and other resolution enhancement technologies (RET) are also a critical aspect of improving manufacturability. Integrating RET-friendly design styles will not only reduce RET layout-processing complexity and mask-making cycle time and cost, it will also ensure best silicon performance. DFM RET recommendations include using rectangular line-ends, forbidding circular or oval shapes, and avoiding short-cropped corners, small zig-zags and jogs, and certain pitches.
Price and Availability
DFM standard cell SIP is available from Prolific today and starts at $25,000 for 100 cells -- $100,000 for 500 cells and is pre-optimized for 130nm and 90nm process technologies, customer design requirements (performance, power, area) and yield. The Prolific DFM SIP is integrated with the Prolific ProGenesis(R) layout generation tool, the Circuit Semantics DynaCell(TM) characterization tool and the Legend Design Technology MSIM(TM) circuit simulator, providing a completely automated solution for the optimization of semiconductor intellectual property.
About Legend Design Technology
Legend Design Technology, Inc. is a leading provider of characterization and simulation software for semiconductor Intellectual Property (IP) in SoC designs. With an emphasis on productivity and value, the company's CharFlo-Memory!(TM) software revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM(TM) and Turbo-MSIM(TM) are the next-generation circuit simulators architected for deep-submicron and nanometer technology challenges. Legend Design Technology is headquartered at 2880 Lakeside Drive, Suite 101, Santa Clara, California 95054, telephone 408-748-8888; fax 408-748-8988. For more information, visit http://www.legenddesign.com.
About Circuit Semantics
Circuit Semantics, Inc. provides electronic design automation (EDA) software that supports precise, gate-level abstraction and analysis of transistor-level circuits, and accelerates timing closure for designs fabricated in nanometer process technologies. Circuit Semantics is headquartered at 2410 Charleston Road, Mountain View, CA 94043, telephone 650-564-9100; fax 650-564-9694. For more information, visit http://www.circuitsemantics.com.
About Prolific
Based in Silicon Valley, Prolific Inc. provides software to enable the design of today's most demanding integrated circuits optimizing quality of results with respect to timing, power, area and yield, and at the same time reducing overall design time and costs. ProTiming(TM) is the first commercially available optimization tool integrated into the STA step of the physical design flow. ProTiming gives IC designers up to 20% improvement in timing and power in a no-risk, fully automated and integrated flow. ProGenesis(R) is the leading software for automatically creating standard cells optimized for design performance, power, area and yield. Founded in 1995, Prolific counts the top semiconductor companies around the world as customers with products silicon proven in .18m through 90nm process nodes. Prolific is headquartered in Newark, Calif., at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone (510) 252-0490, fax (510) 252-0491. For more information, visit www.prolificinc.com.
ProGenesis is a registered trademark and ProTiming is a trademark of Prolific Inc.
DynaCell is a trademark of Circuit Semantics, Inc.
CharFlo-Memory!, Turbo-MSIM and MSIM are trademarks of Legend Design Technology, Inc.
Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
Prolific Dan Nenni, 510-252-0490 X16 Email Contact or ValleyPR Georgia Marszalek, 650-345 7477 (Circuit Semantics) Email Contact or Legend Design Technology Jane Wei, 408-748-8888 X-234 Email Contact