2.12 References

Page numbers in brackets after a reference indicate its location in the chapter body.

Bedrij, O. 1962. “Carry select adder.” IRE Transactions on Electronic Computers , vol. 11, pp. 340–346. Original reference to carry-select adder. See also [Weste, 1993] p. 532. [p. 84]

Booth, A. 1951. “A signed binary multiplication technique.” Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, pt. 2, pp. 236–240. Original reference for the Booth-encoded multiplier. See also Swartzlander [1990] and Weste [1993, pp. 547–554]. [p. 91]

Brent, R., and H. T. Kung. 1982. “A regular layout for parallel adders.” IEEE Transactions on Computers, vol. 31, no. 3, pp. 260–264. Describes a regular carry-lookahead adder. [p. 84]

Brodersen, R. (Ed.). 1992. Anatomy of a Silicon Compiler. Boston: Kluwer, 362 p. ISBN 0-7923-9249-3. TK7874.A59.

Campbell, S. 1996. The Science and Engineering of Microelectronic Fabrication. New York: Oxford University Press, 536 p. ISBN 0-19-510508-7. TK7871.85.C25. [p. 116]

Cavanagh, J. J. F. 1984. Digital Computer Arithmetic Design and Implementation . New York: McGraw-Hill, 468 p. QA76.9.C62.C38. ISBN 0070102821.

Chandrakasan A. P., and R. Brodersen. 1995. Low Power Digital CMOS Design . Boston: Kluwer, 424 p. ISBN 0-7923-9576-X. TK7871.99.M44C43.

Chang, C. Y., and S. M. Sze. 1996. ULSI Technology. New York: McGraw-Hill, 726 p. ISBN 0070630623.

Chen, C. H. (Ed.). 1992. Computer Engineering Handbook. New York: McGraw-Hill. ISBN 0-07-010924-9. TK7888.3.C652. Chapter 4, “Computer arithmetic,” by E. E. Swartzlander, pp. 20, contains descriptions of adder, multiplier, and divider architectures.

Chen, J. Y. 1990. CMOS Devices and Technology for VLSI. Englewood Cliffs, NJ: Prentice-Hall, 348 p. ISBN 0-13-138082-6. TK7874.C523.

Dadda, L. 1965. “Some schemes for parallel multipliers.” Alta Frequenza , vol. 34, pp. 349–356. The original reference to the Dadda multiplier. This paper contains some errors in the diagrams for the multipliers; some remain in the reprint in Swartzlander [1990, vol. 1]. See also sequel papers: L. Dadda and D. Ferrari, “Digital multipliers: a unified approach,” Alta Frequenza, vol. 37, pp. 1079–1086, 1968; and L. Dadda, “On parallel digital multipliers,” Alta Frequenza, vol. 45, pp. 574–580, 1976. [p. 92]

Denyer, P. B., and D. Renshaw. 1985. VLSI Signal Processing: A Bit-Serial Approach. Reading, MA: Addison-Wesley, 312 p. ISBN 0201144042. TK7874.D46. See also P. B. Denyer and S. G. Smith, Serial-Data Computation. Boston: Kluwer, 1988, 239 p. ISBN 089838253X. TK7874.S623. [p. 88]

Diaz, C. H., et al. 1995. Modeling of Electrical Overstress in Integrated Circuits. Norwell, MA: Kluwer Academic, 148 p. ISBN 0-7923-9505-0. TK7874.D498. Includes 101 references. Introduction to ESD problems and models.

Ferrari, D., and R. Stefanelli. 1969. “Some new schemes for parallel multipliers.” Alta Frequenza, vol. 38, pp. 843–852. The original reference for the Ferrari–Stefanelli multiplier. Describes the use of 2-bit and 3-bit submultipliers to generate the product array. Contains tables showing the number of stages and delay for different configurations. [p. 93]

Gajski, D. D. (Ed.). 1988. Silicon Compilation. Reading, MA: Addison-Wesley, 450 p. ISBN 0-201-109915-2. TK7874.S52.

Goldberg, D. 1990. “Computer arithmetic.” In D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 2nd ed., 1995. QA76.9.A73. P377. ISBN 1-55860-329-8. See also the first edition of this book (1990).

Haskard, M. R., and I. C. May. 1988. Analog VLSI Design: nMOS and CMOS. Englewood Cliffs, NJ: Prentice-Hall, 243 p. ISBN 0-13-032640-2. TK7874.H392.

Hwang, K. 1979. Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 423 p. ISBN 0471034967. TK7888.3.H9.

Katz, R. H., 1994. Contemporary Logic Design. Reading, MA: Addison-Wesley, 699 p. ISBN 0-8053-2703-7.

Keutzer, K., S. Malik, and A. Saldanha. 1991. “Is redundancy necessary to reduce delay?” IEEE Transactions on Computer-Aided Design, vol. 10, no. 4, pp. 427–435. Describes the carry-skip adder. The paper describes the redundant logic that is added in a carry-skip adder and how to remove it without changing the function or delay of the circuit. [p. 83]

Lehman, M., and N. Burla. 1961. “Skip techniques for high-speed carry-propagation in binary arithmetic units.” IRE Transactions on Electronic Computers, vol. 10, pp. 691–698. Original reference to carry-skip adder. [p. 83]

MacSorley, O. L. 1961. “High speed arithmetic in binary computers.” IRE Proceedings, vol. 49, pp. 67–91. Early reference to carry-lookahead adder. Reprinted in Swartzlander [1990, vol. 1]. See also Weste [1993, pp. 526–529]. [p. 84]

Mead, C. A. 1989. Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, p.371. ISBN 0-201-05992-4. QA76.5.M39. Includes a description of MOS device operation.

Muller, R. S., and T. I. Kamins. 1977. Device Electronics for Integrated Circuits. New York: Wiley, p. 404. ISBN 0-471-62364-4. TK7871.85.M86. See also the second edition of this book (1986).

Mukherjee, A. 1986. Introduction to nMOS and CMOS VLSI Systems Design. Englewood Cliffs, NJ: Prentice-Hall, 370 p. ISBN 0-13-490947-X. TK7874.M86.

Rabaey, J. 1996. Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, pp. 700. ISBN 0-13-178609-1. TK7874.65.R33. Chapters 4 and 7 describe the design of full-custom CMOS datapath circuits.

Ranganathan, N. (Ed.). 1993. VLSI Algorithms and Architectures: Fundamentals. New York: IEEE Press, 305 p. ISBN 0-8186-4390-0. TK7874.V5554. See also N. Ranganathan (Ed.), 1993. VLSI Algorithms and Architectures: Advanced Concepts. New York: IEEE Press, 303 p. ISBN 0-8186-4400-1. TK7874.V555. Collections of articles mostly from Computer and IEEE Transactions on Computers.

Sato, T., et al . 1992. “An 8.5 ns 112-b transmission gate adder with a conflict-free bypass circuit.” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 657–659. Describes an implementation of a carry-bypass adder. [p. 82]

Sklansky, J. 1960. “Conditional-sum addition logic.” IRE Transactions on Electronic Computers, vol. 9, pp. 226–231. Original reference to conditional-sum adder. Several texts have propagated an error in the spelling of Sklansky (two k’s). See also [Weste, 1993] pp. 532–533; A. Rothermel et al ., “Realization of transmission-gate conditional-sum (TGCS) adders with low latency time,” IEEE Journal of Solid-State Circuits, vol. 24, no. 3, 1989, pp. 558–561; each of these are examples of adders based on Sklansky’s design. [p. 86]

Swartzlander, E. E., Jr. 1990. Computer Arithmetic. Los Alamitos, CA: IEEE Computer Society Press, vols. 1 and 2. ISBN 0818689315 (vol. 1). QA76.6.C633. Volume 1 is a reprint (originally published: Stroudsberg, PA: Dowden, Hutchinson & Ross). Volume 2 is a sequel. Contains reprints of many of the early (1960–1970) journal articles on adder and multiplier architectures.

Sze, S. (Ed.). 1988. VLSI Technology. New York: McGraw-Hill, 676 p. ISBN 0-07-062735-5. TK7874.V566. Edited book on fabrication technology.

Trontelj, J., et al. 1989. Analog Digital ASIC Design. New York: McGraw-Hill, 249 p. ISBN 0-07-707300-2. TK7874.T76.

Uyemura, J. P. 1992. Circuit Design for CMOS VLSI. Boston: Kluwer, 450 p. ISBN 0-7923-9184-5. TK7874.U93. See also: J. P. Uyemura, 1988, Fundamentals of MOS Digital Integrated Circuits, Reading, MA: Addison-Wesley, 624 p. ISBN 0-201-13318-0. TK7874.U94. Includes basic circuit equations related to NMOS and CMOS logic design.

Wakerly, J. F. 1994. Digital Design: Principles and Practices . 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 840 p. ISBN 0-13-211459-3. TK7874.65.W34. Undergraduate level introduction to logic design covering: binary arithmetic, CMOS and TTL, combinational logic, PLDs, sequential logic, memory, and the IEEE standard logic symbols.

Wallace, C. S. 1960. “A suggestion for a fast multiplier.” IEEE Transactions on Electronic Computers, vol. 13, pp. 14–17. Original reference to Wallace-tree multiplier. Reprinted in Swartzlander [1990, vol. 1]. [p. 91]

Waser, S., and M. J. Flynn. 1982. Introduction to Arithmetic for Digital Systems Designers . New York: Holt, Rinehart, and Winston, 308 p. ISBN 0030605717. TK7895.A65.W37. [p. 116]

Weste, N. H. E., and K. Eshraghian. 1993. Principles of CMOS VLSI Design: A Systems Perspective. 2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN 0-201-53376-6. TK7874.W46. Chapter 5 covers CMOS logic gate design. Chapter 8 covers datapath elements. See also the first edition of this book. [p. 82]

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