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[ Chapter start ] [ Previous page ] [ Next page ] 9.2 Low-Level Design LanguagesSchematics can be a very effective way to convey design information because pictures are such a powerful medium. There are two major problems with schematic entry, however. The first problem is that making changes to a schematic can be difficult. When you need to include an extra few gates in the middle of a schematic sheet, you may have to redraw the whole sheet. The second problem is that for many years there were no standards on how symbols should be drawn or how the schematic information should be stored in a netlist. These problems led to the development of design-entry tools based on text rather than graphics. As TTL gave way to PLDs, these text-based design tools became increasingly popular as de facto standards began to emerge for the format of the design files. PLDs are closely related to FPGAs. The major advantage of PLD tools is their low cost, their ease of use, and the tremendous amount of knowledge and number of designs, application notes, textbooks, and examples that have been built up over years of their use. It is natural then that designers would want to use PLD development systems and languages to design FPGAs and other ASICs. For example, there is a tremendous amount of PLD design expertise and working designs that can be reused. In the case of ASIC design it is important to use the right tool for the job. This may mean that you need to convert from a low-level design medium you have used for PLD design to one more appropriate for ASIC design. Often this is because you are merging several PLDs into a single, much larger, ASIC. The reason for covering the PLD design languages here is not to try and teach you how to use them, but to allow you to read and understand a PLD language and, if necessary, convert it to a form that you can use in another ASIC design system. 9.2.1 ABELABEL is a PLD programming language from Data I/O. Table 9.2 shows some examples of the ABEL statements. The following example code describes a 4:1 MUX (equivalent to the LS153 TTL part):
A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15 P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3 P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13 P1Y, P2Y pin 19, 12 "LS153 pins 7,9 P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3); 9.2.2 CUPLCUPL is a PLD design language from Logical Devices. We shall review the CUPL 4.0 language here. The following code is a simple CUPL example describing sequential logic: IF car NEXT green OUT go; /* conditional synchronous output */ DEFAULT NEXT red; /* default next state */ NEXT red; } /* unconditional next state */ This code describes a state machine with two states. Table 9.3 shows the different state machine assignment statements.
You may also encode state machines as truth tables in CUPL. Here is another simple example: TABLE input => output {00 => 01; 01 => 02; 10 => 04; 11 => 08; } The advantage of the CUPL language, and text-based PLD languages in general, is now apparent. First, we do not have to enter the detailed logic for the state decoding ourselves—the software does it for us. Second, to make changes only requires simple text editing—fast and convenient. Table 9.4 shows some examples of CUPL statements. In CUPL Boolean equations may use variables that contain a suffix, or an extension , as in the following example: output.ext = (Boolean expression); The extensions steer the software, known as a fitter , in assigning the logic. For example, a signal-name suffix of .OE marks that signal as an output enable. Here is an example of a CUPL file for a 4-bit counter placed in an ATMEL PLD part that illustrates the use of some common extensions: pin 1 = CLK; pin 3 = LD_; pin 17 = RST_; pin [18,19,20,21] = [I0,I1,I2,I3]; pin [4,5,6,7] = [Q0,Q1,Q2,Q3]; Q3.T = (!Q2 & !Q1 & !Q0) & LD_ & RST_ /* count down */ Q2.T = (!Q1 & !Q0) & LD_ & RST_ # Q2 & !RST_ # (Q2 $ I2) & !LD_; Q1.T = !Q0 & LD_ & RST_ # Q1 & !RST_ # (Q1 $ I1) & !LD_; Q0.T = LD_ & RST_ # Q0 & !RST_ # (Q0 $ I0) & !LD_; CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0; In this example the suffix extensions have the following effects: .CK marks the clock; .T configures sequential logic as T flip-flops; .OE (wired high) is the output enable; .AR (wired low) is the asynchronous reset; and .SP (wired low) is the synchronous preset. Table 9.5 shows the different CUPL extensions.
The 4-bit counter is a very simple example of the use of the Atmel ATV2500B. This PLD is quite complex and has many extra “buried” features. In order to use these features in CUPL (and ABEL) you need to refer to special pin numbers and node numbers that are given in tables in the manufacturer’s data sheets. You may need the pin-number tables to reverse engineer or convert a complicated CUPL (or ABEL) design from one format to another. Atmel also gives skeleton headers and pin declarations for their parts in their data sheets. Table 9.6 shows the headers and pin declarations in ABEL and CUPL format for the ATMEL ATV2500B. 9.2.3 PALASMPALASM is a PLD design language from AMD/MMI. Table 9.7 shows the format of PALASM statements. The following simple example (a video shift register) shows the most basic features of the PALASM 2 language:
CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 /RST VCC STRING Load 'LD*/REV*/CURS*RST' ; load data STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB /Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST /Q1 := /D1*Load+D1*LoadInv:+:/Q2*Shift+RST /Q2 := /D2*Load+D2*LoadInv:+:/Q3*Shift+RST /Q3 := /D3*Load+D3*LoadInv:+:/Q4*Shift+RST /Q4 := /D4*Load+D4*LoadInv:+:/Q5*Shift+RST /Q5 := /D5*Load+D5*LoadInv:+:/Q6*Shift+RST /Q6 := /D6*Load+D6*LoadInv:+:/Q7*Shift+RST /Q7 := /D7*Load+D7*LoadInv:+:Shift+RST; The order of the pin numbers in the previous example is important; the order must correspond to the order of pins for the DEVICE . This means that you probably need the device data sheet in order to be able to translate a design from PALASM to another format by hand. The alternative is to use utilities that many PLD and FPGA companies offer that automatically translate from PALASM to their own formats. [ Chapter start ] [ Previous page ] [ Next page ] | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
