11.14   Summary

TABLE 11.13    Verilog on one page.

  Verilog feature

Example

Comments

a = 0; // comment ends with newline
/* This is a multiline or block
comment */

Constants: string and numeric

parameter BW = 32 // local, use BW
`define G_BUS 32 // global, use `G_BUS
4'b2  1'bx

Names (case-sensitive, start with letter or '_')

_12name  A_name    NotSame  notsame 

Two basic types of logic signals: wire and reg

wire myWire; reg myReg;

Use a continuous assignment statement with wire

assign myWire = 1;

Use a procedural assignment statement with reg

always myReg = myWire;

Buses and vectors use square brackets

reg [31:0] DBus; DBus[12] = 1'bx;

We can perform arithmetic on bit vectors

reg [31:0] DBus; DBus = DBus + 2;

Arithmetic is performed modulo 2 ⁿ

reg [2:0] R; R = 7 + 1; // now R = 0

Operators: as in C (but not ++ or - -)

Fixed logic-value system

1, 0, x (unknown), z (high-impedance)

Basic unit of code is the module

module bake (chips, dough, cookies);
input chips, dough; output cookies;
assign cookies = chips & dough;
endmodule

Ports

input or input/output ports are wire

output ports are wire or reg

Procedures model things that happen at the same time

and may be sensitive to an edge, posedge,  negedge,

or to a level.

always @rain sing; always @rain dance;
always @(posedge clock) D = Q; // flop
always @(a or b) c = a & b; // and gate

Sequential blocks model repeating things:

always: executes forever

initial: executes once only at start of simulation

initial born;
always @alarm_clock begin : a_day
metro=commute; bulot=work; dodo=sleep;
end

Functions and tasks

function ... endfunction
task ... endtask

Output

("a=%f",a);;(a)

Control simulation

;  // sudden or gentle halt

Compiler directives

`timescale 1ns/1ps // units/resolution

Delay

#1 a = b;  // delay then sample b

a = #1 b;  // sample b then delay