Grenoble, France -- October 26, 2012 -- Dolphin Integration today announced the development of a complete platform on the TSMC 180nm eLL process.

Dolphin Integration’s silicon-proven IP to provides value to low power MCU devices targeting the TSMC 180nm eLL technological process.

The foundry sponsored IP includes the sRAM compiler, a 6-track standard cell library, and an Islet Construction Kit. They provide low dynamic power and leakage consumption at 1.8 V together with efficient operation at very low voltage, down to 1.2 V.  Dolphin also provides power regulators for optimal use of these voltage levels.

Both sRAM compiler and standard cell library have been assessed by TSMC’s stringent TSMC-9000TM qualification program.

“The new generation of Low Power MCU devices can now be easily optimized based on Dolphin Silicon IPs and TSMC 180 nm eLL technology”. Said Elsa Bernard-Moulin, Dolphin Integration Marketing Manager for Libraries. “This collaboration with TSMC is a recognition of the quality of our products and Customer support. Our long-term expertise in the design of low power silicon IP has been crucial”.

“Dolphin has been a long-term partner of TSMC to provide foundation IP in TSMC MtM technologies for our customers”, said Dan Kochpatchrin, Deputy Director of IP Portfolio Marketing from TSMC,”

For more information about Dolphin Integration product portfolio and TSMC-9000TM status at 180 nm eLL, feel free to download the Brochure or to contact Elsa BERNARD-MOULIN at ragtime@dolphin.fr


About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, such as mixed signal high-resolution converters for audio and measurement applications, Libraries of memories and standard cells, Power management networks, Microcontrollers. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control. Email Contact