Award Honors Cadence Paper on DRAM IP and Technology

SAN JOSE, Calif. -- 24 Jan 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, received the “Customers’ Choice Award” for its paper on DRAM Interface IP and technology at TSMC’s recent Open Innovation Platform Ecosystem Forum. The paper focused on current and emerging trends in DRAM memories, and the technologies required to enable them. The award marks the second straight year attendees at the TSMC event selected Cadence for the honor. Dean Solov.

In its paper, Cadence demonstrated advanced capabilities in the areas of 3D-IC, hybrid memory cube (HMC), wide I/O and other important DRAM developments. The company highlighted its early development of test chips with TSMC for advanced process nodes and its early IP releases for the newest industry standards.

“The Customers’ Choice Award acknowledges the value of the contributions Cadence is making to bring new DRAM interface technology to market faster,” said Martin Lund, senior vice president, research and development, SoC Realization Group at Cadence. “Working closely with TSMC and our customers, we have developed the IP and technology that serves as a major enabler for early customer adoption of advanced technology.”

“Cadence is helping our customers bring their next-generation technology to market,” said Suk Lee, TSMC senior director of Design Infrastructure Marketing. “Innovation in important areas like memory interface IP can have a significant impact on our customers’ success, and this award is a reflection of that.”