MOUNTAIN VIEW, Calif. – May 29, 2013 – Jasper Design Automation, the leading provider of verification solutions based on state-of-the-art formal technology, will be demonstrating its latest Apps verification solutions in booth #2346 at the Design Automation Conference (DAC), June 2-6, 2013 in Austin, Texas.

Customer seminars at DAC include presentations on:

Sequential Equivalence Verification  

Who: Oski Technologies  

When: Monday, June 3 at 10:00 a.m.

Wednesday, June 5 at 1:30 p.m.

Integrated Flow with ARM

Who: Duolog Technologies and Jasper Design Automation

When: Monday, June 3 at 11:00 a.m. and 3:00 p.m.

Tuesday, June 4 at 10:00 a.m. and 2:30 p.m.

Wednesday, June 5 at 10:00 a.m. and 3:00 p.m.

Security Path Verification

Who: Gila Logic

When: Monday, June 3 at 11:30 a.m.

Wednesday, June 5 at 11:30 a.m.

Adopting Formal to Increase Productivity and Quality in Verification and ARM-Based CPU Subsystem

Who: STMicroelectronics

When: Monday, June 3 at 1:30 p.m.

Tuesday, June 4 at 4:00 p.m.

Formal – An integral Part of Chip Design

Who: Broadcom

When: Tuesday, June 4 at 10:00 a.m.

About Jasper Design Automation

Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on state-of-the-art formal technology.  Customers include worldwide leaders in wireless, consumer, computing, and networking electronics.  Jasper technology has been an integral part of over 150 successful chip deployments.  Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia.  Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity; and accelerate time to market.

Jasper Design Automation and the Jasper Design Automation logo are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.