QuickLogic had identified an opportunity for a high-volume, low-power, low-cost display-bridging solution. Hitting a narrow market window required working with semiconductor development partners with the capabilities to deliver QuickLogic's family of devices within power, size and cost constraints, including:
- Physical design
- Package design
- Foundry execution
- Concurrent package design methodology
"eSilicon's ability to take on a 65nm design quickly to meet our market window was paramount. Additionally eSilicon's full-service back-end capabilities, including in-house expertise in emerging package technology, benefitted the overall project," said Rajiv Jain, senior director of operations, QuickLogic.
eSilicon's package design team determined that a fan-out wafer-level chip-scale package (FOWLCSP) would address the size, power, and cost constraints and provide the following advantages:
- Smaller form factor
- Better electrical and thermal dissipation
- Reduced cost due to denser I/Os and less aggressive foundry rules
- Over-mold for increased reliability
- Simpler supply chain: the substrate house and substrate inventories were no longer needed
- Simpler assembly: the bump interconnect and bond wires were no longer needed
"When we originally planned the device, we selected a wire-bond package, based on certain assumptions. However, MIPI interface constraints, coupled with a disproportionately high number of I/Os on one side of the die, made the wire-bond package impossible to use. We decided to use an FOWLCSP package. After completing a detailed risk assessment, we determined this was the most cost-effective solution to meet market requirements," said Javier DeLaCruz, senior director of engineering, eSilicon.
Concurrent Design Required
However, cost-effective FOWLCSP design requires that package design drives floor planning and pattern layout, including optimizing I/O placement. Although this is challenging when these design functions are outsourced to different suppliers, eSilicon's concurrent design methodology accommodates it easily, resulting in a design that takes advantage of everything this platform has to offer.
For example, eSilicon's package design team placed the I/Os in a ring pattern in order to use a single redistribution layer. This innovative approach resulted in a minimum die size, improved power delivery and reduced foundry and assembly costs.
Foundry Flexibility
Meeting the tight turn-around time required crystal clear communication among the business and technology teams from QuickLogic, eSilicon and GLOBALFOUNDRIES. GLOBALFOUNDRIES also provided a number of manufacturing services to reduce time and risk:
- Early access to ensure a first-time-right prototype and enable a parallel production launch to reduce time to market
- Multi-layer mask for lower prototyping NRE and to quickly get engineering samples to QuickLogic's customers
- Exceptional correlation between silicon results and simulation models
"Collaboration was the hallmark of our engagement with eSilicon and their implementation of QuickLogic's family of display-bridge solutions," said Craig Luhrmann, vice president of channels at GLOBALFOUNDRIES. "eSilicon employed a broad array of skills in optimizing the solution, leveraging GLOBALFOUNDRIES technologies and flexibility."
QuickLogic Display Bridge Family
QuickLogic's ArcticLink III display-bridge solution family uses a 120-ball, 4.5mm x 4.5mm package with a 0.4mm ball pitch. The display bridge solutions enable OEMs to quickly solve processor-display bridging challenges, extend battery life and enhance bright sunlight viewability for mobile applications. QuickLogic's family of display bridges is currently in production.
About eSilicon
eSilicon, the largest independent semiconductor design and manufacturing services provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk path to volume production. eSilicon serves a wide variety of markets including the communications, computer, consumer and industrial segments.
www.esilicon.com.
eSilicon -- Enabling Your Silicon Success™
eSilicon and eSilicon Access are registered trademarks, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
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Contacts: Sally Slemons eSilicon Corporation 408-616-4695 Email Contact Susan Cain Cain Communications 408-393-4794 Email Contact
