TSMC and Cadence have collaborated on a design infrastructure for the 16nm FinFET (16FF) process technology for more than a year. On Tuesday, 11 February at 9am (PST), attend this webinar to learn about the ongoing certification program targeting V1.0 completion, and how Cadence has delivered digital and custom design reference flows and V0.5 certified tools for TSMC’s 16FF process. For early adopters looking to design new devices based on FinFET requirements, TSMC and Cadence have the design infrastructure ready to address all challenges in 16nm design from digital and custom through signoff.

Speakers

• Moderator: Brian Fuller
• TSMC:  Jason Chen— TSMC 16nm Process (pre-recorded)
• Cadence—Cadence 16nm Solution (Live)
  • Digital: Paddy Mamtora
  • Custom: Mladen Nizic
  • Sign-off: Ruben Molina

What You Will Learn

• Advances in the TSMC 16nm FinFET process
• The 16nm FinFET certification timelines from TSMC
• Certified digital and custom 16nm FinFET tools available from Cadence and reference flows available from TSMC
• Additional Cadence® webinars scheduled in Q1 2014 for additional 16nm education

Target Audience

• Designers for TSMC 16nm node

Questions about this event?  Send an email to webinar_info@cadence.com.