SonicsExpress Improves Power Efficiency, Performance and Battery Life in Heterogeneous, Multi-Processor Designs

Milpitas, Calif. – January 28, 2014 – Sonics, Inc., the world’s foremost supplier of on-chip network (NoC) technologies and services, today introduced SonicsExpress™ 2.1, the second generation of its asynchronous bridge intellectual property (IP). SonicsExpress includes a number of new features and capabilities that support dynamic voltage and frequency scaling (DVFS) for system-on-chip (SoC) designs that incorporate multiple power and clocking domains. SonicsExpress delivers highly efficient clock domain crossings for dataflow sockets while minimizing signal and gate count.

“Creation of multi-domain SoC designs is necessary to handle the power and timing requirements of today’s mobile and consumer electronic products where performance and battery life are top concerns,” said Drew Wingard, CTO at Sonics. “Problems frequently arise in these designs when signals must cross between clock and/or voltage domains. We’ve enhanced SonicsExpress to provide the most flexibility and highest quality bridging across boundaries in these heterogeneous, multi-processor designs. The SonicsExpress IP enables SoC designers to use a variety of domain crossing techniques to significantly improve power efficiency and guarantee timing closure while minimizing the silicon area for bridge implementation.”

Today’s SoCs commonly include AMBA® AXI or OCP-compliant interfaces to cross clock and/or power domain boundaries that occur in the design. SoC designers typically develop in-house domain crossing bridges to address problems associated with crossing bundles, but these bridges cannot match the configuration support available in SonicsExpress. With SonicsExpress, the designer precisely specifies the interface configuration and performance required and only incurs the wire and gate cost necessary to meet those specifications.

SonicsExpress generates an optimal bridge instantiation delivered in a proven, high quality implementation that addresses clock domain crossing discipline, power domain crossing discipline, high frequency design discipline, and packaging for ease of physical implementation, all at the same time. Furthermore, SonicsExpress’ new distance spanning capabilities add to its existing timing closure features by wrapping the asynchronous crossing within a synchronous pipeline.

Key features and capabilities in the new version of SonicsExpress include:

• Support of ARM AMBA AXI3 and AXI4 with full support for the AXI Coherency Extensions (ACE)
• Support of cores using the Open Core Protocol (OCP), including a patented, low gate count solution for multi-threaded, non-blocking crossings
• Distance spanning capabilities that ease timing closure challenges
• Automatic clock-gating with fast wakeup and zero un-gated flip-flops for minimum standby (idle) power consumption
• Intelligent start/stop controls to support safe and rapid power-gating for minimum leakage power consumption
• Optimized RTL hierarchy to ease bundling each half of a bridge crossing power domains into the sub-chips implementing each domain.

SonicsExpress 2.1 is available immediately. Contact your Sonics sales representative for more information.

About Sonics, Inc.

Sonics, Inc., is a pioneer of on-chip network (NoC) technology and was the first company to develop and commercialize on-chip interconnect to accelerate volume production of complex, systems-on-chip (SoC) containing multiple processor cores since 1996. Sonics offers SoC designers a comprehensive portfolio of interconnect technologies that deliver the communication performance required by today’s most innovative consumer digital, communications, and information technology devices and electronic products. Sonic’s global customers have shipped more than two billion SoCs and the company holds more than 138 patent properties. Sonics is headquartered in Milpitas, CA, for more information, please visit http://www.sonicsinc.com.