Patented Techniques to Minimize the Die Area, Optimize the Performance, and Raise the Yield Rate

HSINCHU and SANTA CLARA, Calif., April 16, 2014 — (PRNewswire) — Faraday Technology Corporation (TAIEX: 3035), a leading fabless ASIC/SoC and IP provider, today announced the availability of its complete set of cell libraries and memory compilers in UMC 28nm HPM (High Performance for Mobile) and HLP (High-Performance Low Power) processes. Faraday's complete set of 28nm solutions satisfies a wide range of application market requirements featuring low-power, high-density, high-speed, and high yield rate with Faraday's mature methodology. Since launched, they have been recognized and adopted by customers in the market.

Faraday's 28nm cell libraries include 3 series, the 7-track miniLib^TM, the 9-track generic libraries, and the 12-track UHS-Lib^TM. These cell libraries are equipped with the low power management of PSK cells, and multi-Vt and multi-channel length options. Apart from the complete cell library offerings, Faraday's miniLib^TM series takes care of one of the most critical concerns of designers by guaranteeing the same routability while reducing the die size by about 20%. Also, the 12-track UHS-Lib^TM series is developed for optimizing the performance of ARM CPU cores for up to 1.5GHz clock rate.

To mitigate the challenges of process variation associated with advance nodes such as 28nm, Faraday's memory compilers provide users the configurability with different types of assist circuits in order to increase production yield and strengthen chip performance. To improve the write ability for memory cells at low Vcc (supply voltage), a patented and silicon proven NBL (Negative BitLine) technique developed by Faraday is applied. By improving the write ability, NBL is able to increase the production yield even at the worst corner of 28nm HPM process. Furthermore, to increase read margin and improve Vcc-min tolerance by about 200mV, a proprietary tracking control scheme of sensing-margin and a DPRAM cell current booster technique are deployed. Another patented WLUD (Word-Line Under-Drive) technique proves to mitigate the read-disturbance effectively. For ROM memories, Faraday's bit-line leakage suppression and adaptive word-line boost techniques help to increase more read margins.

"From the 20-plus years of dedicated collaboration with UMC in fundamental IP development covering processes from legacy to advanced nodes, Faraday has built a knowledge base second to none with UMC process technologies. This abundant knowhow has always contributed to Faraday's ability to develop highly competitive IP and to attract both IP and ASIC customers, in terms of cell size, performance, power consumption, and yield enhancement," said Eliot Chen, Senior Associate Vice President of RD at Faraday. "With our advantageous partnership with UMC on 28nm solutions, we will keep assisting customers to seize opportunities the moment when they come up in the market," he added.

About Faraday

Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035. For more information, please visit: www.faraday-tech.com

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