Grenoble, France, Sunnyvale, CA – May 6, 2014 – Defacto Technologies, the leading provider of RTL platforms that help achieve early design closure, announced today its unique EDA solution to help build a unified design flow that guarantees coherency between multiple languages and standards: RTL, power intent UPF, IPXACT and SDC.  The unified design flow will be demonstrated at the Design Automation Conference (DAC) held in San Francisco starting June 1, 2014.

“We continue to help chip designers build robust, extensible and custom design flows at RTL. Beyond our RTL editing and structural verification solution, we will be unveiling at DAC new EDA breakthrough technologies in different areas such as RTL “low power” exploration, IPXACT and SDC support,” said Chouki Aktouf, Defacto Technologies co-founder and CEO. “Our unified solution helps SoC designers build coherent and highly maintainable front-end design flows where the construction and the verification of complex RTL designs is automatically linked to different views such as UPF, IPXACT and SDC. With the adoption of Defacto’s EDA unified design flows, key semiconductor companies can truly expect a high degree of maintainability for front-end design flows and drastically decrease engineering costs.”

Defacto team will be presenting its solutions at DAC in booth #807. For presentation and demo requests, please contact Defacto at inforeq@defactotech.com.   

About Defacto 

Defacto Technologies is an innovative chip design software company providing breakthrough RTL platforms to enhance IP integration, design verification and RTL signoff of IP cores and system on chips (SoC). Defacto EDA solutions help solve design problems in areas such as SoC integration, low power, clock verification, RTL signoff, ECO and DFT. Founded in 2003, the company has offices near Grenoble, France, and in Sunnyvale, California, USA, and sales offices in China, Japan, Taiwan, South Korea, Singapore, Israel and Europe. For more information, please visit www.defactotech.com

Acronyms
RTL:      Register Transfer Level 

SoC:      Systems-on-Chip
UPF:     Unified Power Format
SDC:     Synopsys Design Constraint
IPXACT: XML format that defines and describes electronic components and their designs