May 27, 2014 -- Visitors to this year’s Design Automation Conference (DAC) in San Francisco from June 1st to 5th will be able to learn about the most recent research results from the German Fraunhofer Institute IIS/EAS. At this leading conference, it will present the software COSIDE^®, which opens up for developers advanced capabilities in the simulation and modeling of highly complex technical products. Another area of focus will be new methods for the design of interposers for 3D-integrated circuits.

Fraunhofer IIS/EAS will be presenting its current portfolio of solutions for the industry at the world’s most important conference and trade fair for the automated design of electronic systems. Among other things, the researchers will be showing at DAC 2014 the prototype of an interposer that enables the compact arrangement of a processor and wide I/O memory with high bandwidth within an IC. Both are essential for achieving especially high system performance. Developing such a high-performance interposer requires different design procedures than for typical IC components. Fraunhofer IIS/EAS has therefore created a new design flow for the interposer design and 3D integration. In addition, the researchers offer companies support in selecting the right technology for their system integration. With their semi-automated methods, designers can decide already in the early design phases whether an application should best be implemented as a system-in-package, as housing-free chips on silicon interposers or as stacked dies.

Moreover, companies at DAC can witness the high performance of the COSIDE design environment, with which development teams can master the especially high demands of system level design and the challenge of heterogeneous systems that increasingly consist of diverse hardware and software components. COSIDE allows companies to reap the benefits of the free modeling language SystemC as well as its analog extension AMS. The most important new development to be presented by Fraunhofer IIS/EAS at DAC 2014 is the integration of the Universal Verification Methodology (UVM) implementation, making the most powerful verification method currently available compatible with SystemC and SystemC AMS as well.

This makes COSIDE the first software tool in the world that offers such integration. In addition, the design environment has extensive other functions for extremely fast simulation of entire systems with SystemC AMS and verification based on behavior models. The wide range of features offered by COSIDE includes a user-friendly circuit diagram editor and a powerful wave viewer plus the option of IP-protected model exchange and hardware-in-the-loop simulations. The design environment can therefore be coupled and implemented with numerous standard design software tools. Comprehensive modeling support, verification service and customer-specific interfaces round out the portfolio of Fraunhofer IIS/EAS for the design of heterogeneous systems.