Discusses IoT Challenges of Quality, Security and Integration
SAN JOSE, Calif. — (BUSINESS WIRE) — May 30, 2014 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, will showcase the next generation of RTL Signoff solutions at the 51st Design Automation Conference (DAC) to be held June 1-5, 2014 at the Moscone Convention Center in San Francisco, CA. Atrenta’s industry leading RTL Signoff solutions are specifically targeted to handle the difficult challenges in SoC design.
Atrenta will be conducting presentations covering all aspects of its RTL Platform in private suite meetings at DAC. Meeting slots are limited and filling up fast – please visit http://www.atrenta.com/DAC2014/sessions.php for a list of sessions and registration details. Atrenta will also be hosting a panel discussion about the IoT System Design Concerns. This panel will be hosted by EDA veteran Jim Hogan with participation from Atrenta, Cadence, Sonics, and luminary Gary Smith.
“We have expanded our portfolio now with a unique solution for SoC Signoff, built on the success of our IP Signoff solution,” said Piyush Sancheti, vice president of marketing at Atrenta. “Atrenta is helping many SoC design teams worldwide and they are realizing significant productivity gains, including performance and capacity for billion+ gate designs through intelligent abstraction models."
In addition to its show floor activities, Atrenta will participate in a Sunday DAC workshop on IP quality along with IPextreme, TSMC and Sonics. The company will also participate in several Designer and IP Track papers. Atrenta is a sponsor for the Tuesday evening “Stars of IP Party” hosted by IPextreme and its Constellations initiative. The company is also a proud sponsor of the Monday evening HOT Zone, which will raise funds for San Francisco CASA. For all the details of Atrenta’s activities at the 50th DAC, see http://www.atrenta.com/DAC2014/.
About Atrenta Inc.
Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred fifty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
© 2014 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, and Gensys are registered trademarks and BugScope is a trademark of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.
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