Aldec Delivers Complete Coverage Analysis for FPGA and ASIC Designers with the Latest Release of Riviera-PRO

HENDERSON, Nev. — (BUSINESS WIRE) — July 30, 2015Aldec, Inc., announces the latest release of its mixed-language simulator and advanced verification platform, Riviera-PRO™ 2015.06. With the introduction of Condition and Path Coverage, Riviera-PRO now provides a complete coverage analysis package, improving productivity for FPGA and ASIC designers.

Functional coverage and code coverage are two powerful debugging methods that reduce verification time by exposing the areas of a design that require additional testing. This process improves productivity by measuring how much code has been exercised and which parts of any given design have not tested well. In addition, the coverage analysis tools within Riviera-PRO are completely automated, requiring no user intervention or change in the design or testbench.

“The addition of Condition Coverage and Path Coverage features to Riviera-PRO now allows for complete coverage analysis,” said Satyam Jani, Riviera-PRO Product Manager. “Conditional statements such as if-else and case create various paths in the design that divert the stimulus flow in a specific path. Path Coverage enhances the analysis of statement/branch coverage by providing information on completeness of program execution paths. Similarly, Condition Coverage enhances expression coverage data by monitoring and factorizing logical expression used in conditional statements.”

Availability

The 2015.06 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, please visit www.aldec.com/products/riviera-pro.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.



Contact:

Aldec, Inc.
Christina Toole, +1-702-990-4400
Email Contact

Featured Video
Editorial
Jobs
Manufacturing Test Engineer for Google at Prague, Czechia, Czech Republic
Equipment Engineer, Raxium for Google at Fremont, California
Senior Principal Mechanical Engineer for General Dynamics Mission Systems at Canonsburg, Pennsylvania
Mechanical Manufacturing Engineering Manager for Google at Sunnyvale, California
Mechanical Test Engineer, Platforms Infrastructure for Google at Mountain View, California
Machine Learning Engineer 3D Geometry/ Multi-Modal for Autodesk at San Francisco, California
Upcoming Events
FABTECH Orlando 2024 at Orange County Convention Center Orlando FL - Oct 15 - 17, 2024
TIMTOS 2025 at Nangang Exhibition Center Hall 1 & 2 (TaiNEX 1 & 2) TWTC Hall Taipei Taiwan - Mar 3 - 8, 2025
Automate 2025 at Detroit, Michigan, USA MI - May 12 - 15, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise