What:
Afternoon session: Tutorial - Design of ICs using interposers or wafer-level packaging
eSilicon will describe its real-world methodology and experience in designing and manufacturing 2.5D interposers and discuss what can be done to maximize signal and power integrity in 2.5D ASICs.
Who:
Bill Isaacson, eSilicon's director, ASIC product marketing, will present Interposer design and its impact on the system
When:
Tuesday, December 15, 2015
1:10-1:30
Where:
Sofitel San Francisco Bay
223 Twin Dolphin Drive
Redwood City, CA 94065
About 3D ASIP
3D ASIP, now in its 12th year, is firmly established as the leading industry event in 3D integration and packaging. This conference presents a broad, yet thorough perspective on the techno-market opportunities and challenges offered by building devices and systems in the vertical dimension, and provides participants the unique opportunity to gain the latest technology and market insights on 3D integration and packaging efforts, and technology and industry trends impacting this dynamic arena. For more information, visit the
3D ASIP conference website.
About eSilicon
eSilicon guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results.
www.esilicon.com
The right chip. Right now™
Contacts: Sally Slemons eSilicon Corporation 408-635-6409 Email Contact Susan Cain Cain Communications 408-393-4794 Email Contact
