Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has introduced the newest IP Core. The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. It contains USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
Poland, Bytom, October the 17th, 2016. The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. DCD’s IP Core contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
- It supports 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates – explains Tomek Krzyzak, VP of DCD – of course we know that some might ask why not USB 3.0? – but honestly speaking in 99.9% of embedded applications, USB 2.0 is more than enough.
The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
DCD’s USB IP Core portfolio includes also: Audio Platform USB 2.0 - Audio Devices Design Platform, USB 2.0 HID Platform - USB 2.0 Human Interface Devices Design Platform, USB 2.0 MS Platform - USB 2.0 Mass Storage Devices Design Platform, USB 2.0 DUSB2 - USB 2.0 Device Controller USB 2.0 (UTMI interface).
More information: http://dcd.pl/ipcore/1250/dusb2-ulpi/
Key features:
- Full compliance with the USB 2.0 specification
- Full-speed 12 Mbps operation
- High-speed 480 Mbps operation
- Software configurable EP0 control endpoint size 8-64 bytes
- Software configurable 15 IN/OUT endpoints:
- configurable number of endpoints
- configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
- configurable direction of each endpoint
- configurable size of each endpoint: 8-1024 bytes
- Supports ULPI Transceiver Macrocell Interface
- Synchronous RAM interface for FIFOs
- Suspend and resume power management functions
- Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
- Allows operation from a wide range of CPU clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Scan test ready
Information about Digital Core Design:
The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 75 times faster than the standard solution. The same, D32PRO, which is a royalty-free and fully scalable 32-bit CPU creates new possibilities for modern projects. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 500 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.
Contact:
Tomeq Cwienk
PR Manager
Digital Core Design
Web:
www.dcd.pl
Telephone: + 48 32 282 82 66 ext.25
E-mail:
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