MILPITAS, CA--(Marketwired - November 29, 2016) - Open-Silicon, a system-optimized ASIC solution provider, today announced that its president and CEO, Taher Madraswala, will deliver the closing keynote address at the REUSE 2016 Semiconductor IP Tradeshow & Conference on December 1 in Mountain View, CA. Mr. Madraswala will discuss the third-party IP ecosystem and its critical role in the growth of the semiconductor industry. Additionally, Dhananjay Wagh, principal IP architect and innovation manager for Open-Silicon, will present a paper on an HBM2 IP subsystem solution for high bandwidth memory applications. Open-Silicon will also showcase its innovative chip-to-chip and chip-to-memory interface IP solutions, including the Interlaken Controller IP, HMC 2.0 Memory Controller IP and HBM2 IP Subsystem Solution.
REUSE 2016 is the first of an annual conference and trade show intended to bring together the semiconductor IP supply chain and its customers. This free, one-day event is a forum for exchanging ideas, networking and providing IP buyers with the opportunity to meet and obtain in-depth information from a diverse group of suppliers. For more information, please visit www.reuse2016.com
Closing Keynote Address:
- Title: "A Vibrant 3rd Party IP Ecosystem is Critical to the Growth of the Semiconductor Industry"
- Who: Taher Madraswala, President and CEO, Open-Silicon
- When: Thursday, December 1, 2016, 4:30 p.m. - 5:00 p.m.
- Location: Hahn Auditorium, Computer History Museum, Mountain View, CA
- Abstract: The third-party IP ecosystem plays a critical role in the growth of the semiconductor industry. Taher Madraswala, president and CEO of Open-Silicon, will discuss the state of the IP market and how the functional integration of IPs is driving new market applications. He will discuss the importance of choosing the right IPs in order to achieve first time silicon success, as well as the benefits of leveraging third-party IP compared to internal IP development. Taher will describe case studies of complex SoCs, completed for leading OEMs, that were highly successful through leveraging the third-party IP ecosystem. Designers are finding new ways to produce less expensive SoCs with 2.5D interposer based system-in-package (SiP) designs, which enable a mix and match of chip/IP components at optimum process nodes. This approach will greatly increase the reuse of IP developed at older process nodes. Additionally, as IP integration costs are increasing due to the rising number of discrete IP blocks in the current generation of SoCs, designers are leveraging IP subsystem-based design methodologies to lower development cost and risk. Continued developments in the third-party IP ecosystem, for new trends like 2.5D SiP and IP subsystems, will enable the semiconductor industry to continue to innovate and evolve.
Paper Presentation:
- Title: "HBM2 IP Subsystem Solution for High Bandwidth Memory Applications"
- Who: Dhananjay Wagh, Principal IP Architect & Innovation Manager, Open-Silicon
- When: Thursday, December 1, 2016, 2:30 p.m. - 3:00 p.m.
- Location: Boole Room, Computer History Museum, Mountain View, CA
- Abstract: The most common memory requirements for emerging applications, such as high performance computing, networking, deep learning, virtual reality, gaming, cloud computing and data centers, are high bandwidth and density based on real-time random operations. High Bandwidth Memory (HBM2) meets this requirement and delivers unprecedented bandwidth, power efficiency and small form factor. HBM2 (X1024) offers the maximum possible bandwidth of up to 256GBps compared to 4GBps with DDR3 (X16) at 1/3 rd of the power efficiency. HBM2 and 2.5D silicon interposer integration unlock new system architectures, which is causing HBM2 ASIC SiP (system-in-package) to gain popularity among OEMs. One of the key IPs used to develop these ASIC SiPs is the HBM IP subsystem that consists of a controller, PHY and die2die I/O. Mr. Wagh will give an overview of Open-Silicon's new HBM2 IP subsystem, which fully complies with the HBM2 JEDEC® standard and addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging and test, and manufacturing. He will explain how this new architecture enables maximum bandwidth, drives the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer, and holds the key to ramp HBM2 ASIC designs into volume production.
About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers' products by innovating at every stage of design - architecture, logic, physical, system, software and IP - and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 120 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com
Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.
Contact Information: Purvi Shenoy Open-Silicon 408-240-5772 Email contact
Media Contact: Jennifer DeAnda 208-794-7113 Email contact
