EL SEGUNDO, Calif. – Dec. 5, 2016  -- A new application note features NI AWR Design Environment as a unified design environment that streamlines complete multi-chip module design, inclusive of simulation, EM verification and yield optimization, thus enabling designers to not only understand design sensitivities of specific components but also manufacturing tolerances and to compensate for the impact of these variations on the overall design performance. The application note details this process with a dual band, 1.9 GHz (cellular) 2.5 GHz wireless local area network (WLAN) front-end module (FEM) that includes two power amplifiers (GaAs and SiGe), surface-mount bulk acoustic wave (BAW) filters and a laminate substrate.

Where: The Multi-Chip Module Design, Verification, and Yield Optimization application note can be downloaded at http://www.awrcorp.com/resource-library/multi-chip-module-design-verificationand-yield-optimization.


When: Immediately.


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