IEEE EDPS comes to Silicon Valley
Shishpal Rawat, President IEEE Council on EDA
General Chair, EDPS 2017 (Sep 21 & 22)
Aug 10, 2017 -- The 2017 IEEE Electronic Design Process Symposium is in its 24th year and as usual fosters the free exchange of ideas among the top thinkers and thought leaders who focus on how chips and systems are designed in the electronics industry. It provides a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
As designs get more complex, the design, test and manufacturing cycles are getting longer and more intertwined with each other. Therefore EDPS is expanding its scope and looking beyond the classical design processes. EDPS 2017 is adding test, manufacturing and validation issues as they pertain to the design of chips/systems. Each session of EDPS will offer a holistic view of design, test, validation and manufacturing issues.
This year our focus is on accelerating design processes as well as design analysis (CAD/Test/Manufacturing tools). We will look at new developments in systems approach to design and manufacturing and using system level techniques to reach HVM in a shorter amount of time. New techniques such as big data analysis and machine learning for improving design processes as well as the tools will be presented. We have speakers from Intel, Mentor, Ansys, Solido, ARM, PDF Solutions, UltraSoC, Cadence, ASE, Amkor, Test Evolution, Open Silicon, Third Millennium Test Solutions etc. discussing integration of new techniques in their solutions. We also have speakers from UC San Diego, Ga Tech, NC State showcasing how some of the latest research is making it into design and manufacturing processes and associated tools.
Additionally, we have prominent keynotes from industry veterans on design and manufacturing trends and requirements that we will see over next five to ten years. Our keynote speakers are
Antun Domic, CTO, Synopsys: Exploit close relationship of design & manufacturing to accelerate product intro
Zoe Conroy, Sr. Manager, Cisco: Using System level testing as a conduit to HVM
Jim Hogan, Private Investor: EDA industry’s participation in cognitive age: The fourth industrial revolution
Pankaj Mehra, VP, Western Digital: Getting EDA ready for the data centric architecture
The event will be held conveniently at the SEMI facility in Silicon Valley and provide a forum for EDA, design, wafer fab and packaging/test experts to address both design and manufacturing challenges at this event. To register go to http://edps2017.eventbrite.com. Use EDACAFÉ-EDPS code before Aug 31, to receive an additional $50 off of early registration. For a list of speakers and abstracts visit http://edpsieee.ieeesiliconvalley.org/edps_program.php.
