HiSilicon Selects Cadence Tensilica Vision P6 DSP for its Latest Kirin 970 Mobile Application Processor

Tensilica Vision P6 DSP increases imaging/vision performance by up to 4X compared to the highly successful Vision P5 DSP

SAN JOSE, Calif., Nov. 6, 2017 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that HiSilicon, a global fabless semiconductor and IC design company, has selected the Cadence® Tensilica® Vision P6 DSP for its 10nm Kirin 970 mobile application processor, which debuted in Huawei's new Mate 10 Series mobile phones. In deploying the Vision P6 DSP, HiSilicon added valuable imaging and vision processing capabilities to the Kirin SoC.

Cadence Logo. (PRNewsFoto/Cadence Design Systems, Inc.) (PRNewsFoto/CADENCE DESIGN SYSTEMS_ INC_) (PRNewsFoto/CADENCE DESIGN SYSTEMS, INC.)

The high-performance Vision P6 DSP with increased math throughput and other architecture enhancements sets a new standard in imaging and computer vision benchmarks, increasing performance by up to 4X compared to the previous generation Tensilica Vision P5 DSP.  Due to its wide VLIW SIMD architecture, highly optimized instruction set and expertly tuned imaging library, the DSP is an ideal platform for emerging imaging applications such as 3D sensing, human/machine interface, AR/VR and biometric identification for the mobile platform.

"We have a long history of working with the Cadence Tensilica team," said Yanqiu Diao, deputy general manager, Turing Processor Business Unit at HiSilicon. "The Tensilica Vision P6 DSP provides us with the low energy and high efficiency needed for the most innovative imaging applications designed for the mobile platforms of 2018-2019. The software tools and library offered by Cadence allowed us to reduce our development time and achieve our desired performance target in record time."

"With the integration of the Vision P6 DSP into their flagship Kirin 970 mobile application processor for Huawei's latest phone, HiSilicon validates the Vision P6 DSP as their processor of choice when low power and high performance are needed for 3D sensing, human/machine interface and AR/VR applications," said Pulin Desai, product marketing director for imaging and vision, of Cadence. "We are delighted that our long-term relationship and successes with HiSilicon keep us an integral part of their ongoing innovations in mobile and digital media."

The Tensilica Vision P6 DSP is based on the Cadence Tensilica Xtensa® architecture and combines flexible hardware options with a library of vision/imaging DSP functions and numerous vision/imaging applications from established ecosystem partners. It also shares the comprehensive Tensilica partner ecosystem for other application software, emulation and probes, silicon and services, and much more. The Xtensa architecture is one of the most popular licensable processor architectures, shipping in products spanning from sensors to supercomputers.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Cadence Newsroom
408-944-7039
newsroom@cadence.com

View original content with multimedia: http://www.prnewswire.com/news-releases/hisilicon-selects-cadence-tensilica-vision-p6-dsp-for-its-latest-kirin-970-mobile-application-processor-300548805.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com

Featured Video
Editorial
Jobs
Manufacturing Test Engineer for Google at Prague, Czechia, Czech Republic
Equipment Engineer, Raxium for Google at Fremont, California
Mechanical Engineer 3 for Lam Research at Fremont, California
Mechanical Engineer 2 for Lam Research at Fremont, California
Senior Principal Mechanical Engineer for General Dynamics Mission Systems at Canonsburg, Pennsylvania
Mechanical Test Engineer, Platforms Infrastructure for Google at Mountain View, California
Upcoming Events
Celebrate Manufacturing Excellence at Anaheim Convention Center Anaheim CA - Feb 4 - 6, 2025
3DEXPERIENCE World 2025 at George R. Brown Convention Center Houston TX - Feb 23 - 26, 2025
TIMTOS 2025 at Nangang Exhibition Center Hall 1 & 2 (TaiNEX 1 & 2) TWTC Hall Taipei Taiwan - Mar 3 - 8, 2025
Additive Manufacturing Forum 2025 at Estrel Convention Cente Berlin Germany - Mar 17 - 18, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise