February 8, 2019 -- New Space concept is moving fast. Some technology drivers of this evolution are the new communication standards that enables interoperability among spacecraft systems. As an example, the evolution of SpaceWire standard is coordinated by the European Space Agency (ESA) in collaboration with international space agencies including NASA, JAXA, and RKA.
SoCe has released a SpaceWire IP Core is a VHDL core that implements a complete, reliable and fast SpaceWire encoder-decoder with AXI management interface, synthesizable for FPGA and for reconfigurable SoC Devices. It is designed to conform to ECSS-E-ST-50-12C. It is supported on the following Xilinx FPGA Families under Vivado tool:
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
SpaceWire
This IP has been integrated on the electronic platform designed in collaboration with Satlantis to communicate with the satellite on-board computer.
Soce Statlantis Logo
SpaceWire IP has been tested using the following third-party equipment: Star-Dundee SpaceWire PCIe: https://www.star-dundee.com/products/spacewire-pcie
SoCe offers full support on the integration and modification of the IP and works in SpaceWire related projects with different scope up-to the customer.
For more information about this IP, licensing modes and turn-key projects based on this standard, please contact us at: Email Contact.
