Maximizing Design Performance
Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the challenges associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, and pragma insertion location to help engineers prepare and optimize their C/C++ application code for HLS.
"The release of SLX FPGA v19.4 represents another significant step forward in bridging the gap between software development and designing an FPGA," said Jordon Inkeles, VP of Product at Silexica. "Using Xilinx Vivado HLS design flow with Silexica's advanced C/C++ analysis, SLX FPGA provides unmatched insights into application code to help Xilinx's customers maximize their design performance."
SLX FPGA helps enable software developers to save months of development effort by performing:
- Guided and automatic refactoring of non-synthesizable code written in C/C++
- Detecting C/C++ code that can be executed in parallel to optimize performance
- Automatic insertion of optimized pragmas to guide the Vivado HLS compiler
"Design space exploration can be quite difficult with high-level, synthesis-based designs," said Hiroaki Yamashita, Senior Professional Engineer at Fujitsu Kyushu Network Technologies Limited. "SLX FPGA provides insights into our C/C++ applications that allow us to make informed design decisions and help us significantly reduce the amount of time required to complete an HLS-based design."
New features and enhancements to SLX FPGA v19.4 include:
- Support for Arbitrary Precision Integer Data Types provides parallelism detection and analysis tools to support applications that utilize arbitrary precision integers ("ap_int" and "ap_uint"). This enables SLX FPGA v19.4 to perform parallelism detection in loops that use variables for processing, allowing for the generation of pragmas on these loops.
- Improved Synthesizability Checks and Guidance to support C++ specific constructs and warn the user when non-synthesizable code is used. When non-synthesizable constructs are found, SLX FPGA provides guidance for re-writing the code to be synthesizable.
- Function Mapping Editor provides a centralized location that displays the project's functions and their dependencies via a function mapping graph, as well as each function's properties. The new function mapping editor allows for faster design iterations and further enhances the productivity of the engineers using SLX FPGA v19.4.
- Modeling of Platform Interfaces allows the configuration of interfaces and bandwidth that are available to synthesizable (top-level hardware) functions.
- Analysis time improvements reduce the time required for SLX FPGA to analyze users' code, further reducing the development time required to optimize code for HLS.
Please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA.
About Silexica
Silexica provides software development solutions that enable technology companies to take intelligent products from concept to deployment by mastering state-of-the-art computing at the edge. The SLX programming tools analyze how software runs on heterogeneous compute platforms and provide deep system understanding for the developer.
Founded in 2014, Silexica has received $28 million in funding. Headquartered in Germany with offices in the U.S. and Japan, Silexica's team of leading software engineers supports hardware and software engineers in the automotive & ADAS, aerospace & defense, 5G wireless, robotics, and other rapidly transforming industries.
PR Contact:
Jessica Krings
press@silexica.com
www.silexica.com
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SLX FPGA v2019.4
SLX FPGA v2019.4 Delivers an Average of 45X HLS Performance Improvement
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