October 31, 2024 - Laguna Hills, CA - Excellicon Inc., a pioneering provider of comprehensive timing closure solutions, has demonstrated an impressive 3X – 5X improvement in performance across its entire product portfolio, especially the compute intensive verification, with the revolutionary Hyper-Graph Technology.

Excellicon has recognized the significant expansion in design complexity, characterized by a surge in gate count and the proliferation of clock domains. Current timing constraint solutions struggle to manage these large-scale designs without resorting to distributed networking or increasing thread counts, which in turn raises the license count burden for users.

To tackle these challenges, Excellicon has re-engineered its core timing graph engine. The newly developed  Hyper-Graph technology , a native innovation by Excellicon, delivers exceptional speed and memory efficiency to address the needs of growing design sizes which are multiplying in various applications such as AI, consumer, or automotive, etc. This breakthrough results in a 3X-5X run time speed improvement over the nearest competitor, significantly reducing run-times and memory usage as verified by various customers in USA, Europe, Taiwan and Korea across varying design styles.

When it comes to quality of constraints files for sign-off, there are two main considerations. 1) Correct and complete  generation of constraints from design itself which leads to more targeted and effective verification; a unique Excellicon capability 2) Ability to effectively verify constraints against actual design and design versions in a timely and efficient manner. Similarly, the validation time involves both tool performance, efficiency and ease of use in the design flow which is addressed below.

Let us first address the second point; Verification of timing constraints, which entails multiple runs, validating all timing constraints for all layers of a hierarchical design and the ability to check the equivalency of constraints through different layers of hierarchy. Total and Complete Constraints Verification involves not only tracing and rule-based checking of design, but also the ability to formally examine and validate many aspects of rules which may trigger using internal tool intelligence. Such analysis can further result in generation of SVA’s (System Verilog Assertions) which can then be used for inclusion in simulations.

Another aspect of validation is TEC (Timing Equivalence Checking) which is essential when performing any kind of hierarchical promotion or demotion to ensure proper propagation and correctness of all defined constraints. In addition, a widely ignored aspect of Equivalence checking is ability to compare different versions of design to one constraints file (2D1S), or a multiple constraints file against a single design (2D1S), or even multiple constraints file against different constraints files (2D2S). Designers are also able to compare gate level design against the RTL version of the design with a given constraints file, in addition to other variations. Timing Equivalence Checks (TEC) essentially closes a gap on the timing front, which has been covered on the functional side by functional equivalency tools; LEC.

Bug avoided early on is a bug not needed to be caught or verified. The first point mentioned above is about Excellicon’s comprehensive end-2-end correct-by-construction solution designed to generate and validate the timing constraints, based on the actual design database to ensure high quality timing constraints generation.

In the past, verification execution time has significantly limited comprehensive analysis. However, with the integration of Hyper-Graph Technology and multi-threading across any number of cores, comprehensive analysis is now achievable. This advancement not only enhances tool capabilities in post-processing information but also ensures timely results. Excellicon's cutting-edge innovation now makes full verification of constraints for large SOCs or IPs a practical reality.

Back to the first point listed above, Generation is an essential feature required for complete and correct hierarchical constraints promotion which differentiates Excellicon patented timing constraints promotion method from any other competing solutions. Correct and Complete Constraints generation essentially helps in reduction in verification tasks while helping to shorten the timing constraints verification cycles. The promotion capability simply enables designers to automate many manual and tedious tasks with automated formal and static analysis to ensure proper validation and propagation of timing constraints across layers of hierarchy.

When it comes down to checking the feature boxes and comparing timing constraints tools on paper, verification is one box that is always checked by all vendors and available tools in the market, however the designer experience reality is much different from check boxes. Of course, the devil as always is in the details. When compared side-by-side. Excellicon has consistently come out on top with order of magnitude run time improvement and opportunity to eliminate many iterations and manual interventions which typically wastes weeks of design time. The innovative Hyper-Graph Timing Technology enables designers to further gain a significant advantage in analyzing designs much more comprehensively. In many cases we engage with designers who are frustrated with manual intervention needed using any of the traditional tools involving in hierarchy delimiter manipulation and/or blind tracing of paths which results in high number of warnings and errors being generated without proper analysis. In our experience integration of legacy products into new environment by our competitors has only proven to be much more costly on compute resources and memory foot print, not to mention designer experience and turnaround time”; said Rick Eram, VP of Sales and Marketing at Excellicon.

About Excellicon

Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Early design planning and debugging solutions automating constraints, authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Additionally, Excellicon products are targeting early design planning and viability analysis helping to detect design implementation issues very early on. Excellicon products are Constraints Manager (ConMan), Constraints Certifier (ConCert), Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (TEC), ConStruct Early design Planning, ConTree clock tree verification & Optimization, and ConTour address the needs of designers at every stage of SOC design and implementation in a unified environment. – Design & Timing Closure; Done Once! Done Right!