New Methodology Speeds Hardware and Software Design and IP Reusability
"Today's design teams are looking for methods to manage changes between the chip specifications and all the implementations used throughout the design and verification process," states Jennifer Sirrine, senior design engineering manager at Cypress Semiconductor. "Our engineering teams wanted a single source for control register descriptions, and by using the industry-standard SystemRDL and Blueprint, have realized reduced integration time enabling us to meet our design requirements. Denali's Blueprint provides Cypress with an integral and reliable platform solution for SoC design."
Cypress PSoC devices employ a highly configurable system-on-chip architecture for embedded control design, offering a flash-based equivalent of a field-programmable ASIC without lead-time or NRE penalties. PSoC devices integrate configurable analog and digital circuits, controlled by an on-chip microcontroller, providing both enhanced design revision capability and component count savings. They include up to 32 Kbytes of Flash memory, 2 Kbytes of SRAM, an 8x8 multiplier with 32-bit accumulator, power and sleep monitoring circuits, and hardware I2C communications. For more of PSoC information, visit: www.cypress.com.
"Denali understands the challenges facing design teams today. The control register content has exploded in modern SoC's with numbers of control registers often exceeding 10,000 instances," states Sean Smith, director of Field Applications and product manager for Blueprint at Denali Software. "Our customers, such as Cypress, can utilize SystemRDL to specify all the control register content and act as a single source of information, and then with Blueprint Compiler, generate all control registers and related content such as documentation, RTL implementations, and verification test cases. Due to this automated synchronization, Blueprint results in increased chip design productivity and speeds IP reuse."
About Denali Blueprint
Denali Blueprint, now part of PureView(TM) and MMAV(TM) 2008, is a SystemRDL compiler that enables a system-level approach to automating specification, view generation, and management of control registers for IP and SoC design. Blueprint will generate necessary outputs and views for design, verification, documentation, software development, post silicon debug and even enables early software development with SystemC(TM) Transaction Level Models. Blueprint guarantees interoperability with other EDA tools by inputting and outputting IP-XACT and SystemRDL formats. For more information about Blueprint and its architectural benefits, visit: www.denali.com/blueprint.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Blueprint, MMAV, and PureView are trademarks of Denali Software, Inc. All other trademarks are of their respective owners.
Editorial contact:
Pierre Golde
Denali Software, Inc.
(408) 743-4262
pgolde@denali.com
Web site: http://www.denali.com//
