First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications
"We are pleased to see member companies introduce next-generation technologies that fully support the LPDDR2 industry specification. It is this type of advanced industry adoption that helps to establish high quality and reliability benchmarks required for low power and embedded system memory design," said Roger Isaac, chair for the JEDEC JC-42.6 Low Power Memory Committee. "Denali is an active committee participant, working closely with memory vendors like Spansion to provide valuable recommendations toward the development of the specification."
Denali's LPDDR2 memory controller and PHY will support the full specification when released by JEDEC. LPDDR2 addresses the needs of mobile and consumer systems where the "PC memory" devices, DDR2 and DDR3, are unsuitable, as LPDDR2 offers a low power, low voltage, low pin-count memory in a range of densities and speeds that are closely matched to the needs of those mobile and consumer systems. In addition, LPDDR2 was designed to allow sharing of SDRAM and NVM memory on the same bus, which is extremely difficult in PC memory technologies. For immediate availability of a C-model, in advance of the silicon IP for Denali's Databahn LPDDR2 memory controller and PHY, contact Email Contact.
"Many of our customers are looking for ways to upgrade to new controller technologies and are faced with several challenges," states Marc Greenberg, director of Technical Marketing for Databahn products at Denali Software. "Many of the LPDDR2 features are derived from the best features of the LPDDR1, DDR2 and DDR3 technologies that we already support. This gives Denali an accelerated position to support the LPDDR2 architecture and continue to provide our customers with high-quality, interoperable, and configurable IP solutions."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon-specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://www.denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.
Editorial contact:
Pierre Golde
Denali Software, Inc.
(408) 743-4262
pgolde@denali.com
Web site: http://www.denali.com/
