USB-Xactor is a complete verification solution consisting of SystemVerilog OVM/VMM compliant Bus Functional Models (BFM), protocol checkers, directed and random compliance test suites, and reference verification frameworks. The USB-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their Superspeed compliant host, hub, and device controller-based designs.
“USB-Xactor builds on our solid foundation as a leading supplier of PCI Express, Serial ATA, and Parallel ATA verification solutions to IP vendors and semiconductor companies,” said Chris Browy, vice president of sales and marketing of Avery Design Systems. “Our compliance solution enables designers to thoroughly verify the new link and physical layers of the Superspeed standard and effectively pinpoint areas of non-compliance.”
Key Features
- Host model performs bus enumeration and and allocates independent USB pipes for communication flows between host and each device endpoint
- Program models for TP sequences for Bulk, Isochronous, Interrupt, Bulk Stream, and Control (Device request) transfer types
- Program USB Device requests to access USB device descriptors
- Automatic frame scheduling and bus interval and service interval support including ITP generation
- Program and send raw protocol layer packets
- Program USB host and device model timing parameters and response behaviors such as link commands
- Automatic flow control
- Fine-grained control over LTSSM transition sequences
- Fine-grained link layer controls
- Inject errors at all layers through callbacks
- Control device operations state transitions including suspend/resume
- Full power management support (U0-U3) including automatic and software directed entry/exit
- PowerOn and Inband reset
Key BFM Features
- Layered environment based on family of SystemVerilog classes and methods
- Abstract data model for transfer, packet, and descriptor types
- Drivers, event callbacks, and scoreboard options automate status and result checking
- Random scenario generation with constraints stress design operation
- Directed tests for focused functional compliance testing
- Functional coverage monitoring of scenario cases
- Comprehensive protocol checking
- VMM/OVM support
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for PCI Express, SATA, and USB standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with Rambus, GDA Technologies, Snowbush, and CAST. More information about the company may be found at www.avery-design.com.
Contact:
Avery Design Systems
Chris Browy, 978-689-7286
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