TOKYO—(BUSINESS WIRE)—February 10, 2009— Toshiba Corporation (TOKYO:6502) today announced breakthroughs in multi-bit-per-cell technology for NAND flash memories that will bring advances in chip densities and cost savings to next generation devices. In the 32 nanometer (nm) generation, Toshiba has realized a 3-bit-per-cell 32 gigabit (Gb) chip with the world-smallest die size, and smaller than a 2-bit-per-cell 16Gb chip fabricated with 43nm technology, which is currently in the market. The cutting-edge chip will be mass produced in the second half of CY2009. The company has also fabricated the world’s first 64Gb chip that applies 4-bit-per-cell technology at the 43 nm process generation.

Toshiba and its technology partner, SanDisk, unveiled these key technology advances today at the International Solid State Circuits Conference (ISSCC) now underway in San Francisco, California.

Manufacturers of NAND flash memories must respond to demand for higher density with lower costs. Toshiba and SanDisk have done so through the application of its innovative technologies.

The 3-bit-per-cell 32nm generation device uses optimized circuit design for the row decoder and extended column architecture, which significantly contributed to a 113mm² chip, the smallest die size yet achieved in this generation. The 4-bit-per cell applies super multi-bit programming technologies, which realizes 64Gb without increase in chip size, while achieving a write speed performance of 7.8MB/s.

Toshiba and SanDisk have maintained their continuing leadership in the development and manufacturing of advanced NAND flash memory. Toshiba will promote further development in leading-edge process technologies to further widen the scope of application and to expand the NAND flash memory market.

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Contact:

Toshiba Corporation
Kaori Hiraki, +81-3-3457-2105
Corporate Communications Office
http://www.toshiba.co.jp/contact/media.htm