- Layered environment based on family of SystemVerilog classes and methods
- Abstract data model for transfer, packet, and descriptor types
- Drivers, event callbacks, and scoreboard options automate status and result checking
- Robust error injection enables modifying, adding, or deleting frames
- UFS and UniPro transaction trackers (command and packet exchanges)
- Throughput calculation for performance analysis
- Random scenario generation with constraints stress design operation
- Directed tests for focused functional compliance testing including UFS and SCSI commands and UFS and UniPro power modes
- Functional coverage monitoring of scenario cases
- Comprehensive protocol checking
- UVM support
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, NVM Express, SCSI Express, SATA Express, eMMC, and SD/SDIO standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Contact:
Avery Design Systems
Chris Browy, 978-689-7286
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