LIVE WEBINAR: VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment 9:12 AM

Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.

 

What about Verilog and SystemVerilog? It is clear from the Wilson Verification survey that VHDL is the preferred FPGA design language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.  

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