PowerMiser AI is optimised for low dynamic power to cut thermal load in Large Language Model Applications

Sheffield, England, 7 March 2024 – CES 2024 showed how AI is becoming pervasive in a huge range of products making them smarter, safer and feature rich. To run these AI workloads requires significant compute power which in turn requires considerable amounts of embedded memory integrated on chip as close to the compute units as possible to reduce latency. Delivering the inferencing power that users now expect requires massively parallel processing arrays which means not only increased power consumption, but also ever challenging thermal loads placing demands on packaging and cooling needs. SureCore has revisited its PowerMiser IP and further optimised it to drive down dynamic power further as well as exploiting the power efficiencies of FinFET technology. This has delivered a memory technology that minimises thermal impact whilst delivering the demanding performance profile needed by AI and has called it “PowerMiser AI”.

Paul Wells, sureCore’s CEO, explained, “Our typical customer has been using our ultra-low power SRAM IP in battery-powered applications to provide a longer operational life between recharges. The surge in AI augmentation means that whole new areas for our low power memory solutions have appeared in new and exciting areas that are not constrained by battery life and can be mains powered or are even in the automotive space. Power consumption is still a critical factor for these applications but the constraining factor is starting to become heat dissipation and potential thermal damage. In order to keep product form factors under control and obviate the need for forced cooling so as to prevent overheating, new low power solutions are needed. Our recent announcements about working on ultra-low power memory IP for use in cryostats in the quantum computing arena, where heat generation by chips has to be minimised, has resulted in enquiries from companies who also need to keep AI chips operating within temperature boundaries albeit at the other end of the scale.

“Standard off-the-shelf SRAM IP has been optimised for area or speed, but not power.  Our technology is extremely power efficient and therefore generates less heat making it the ideal solution for the next generation of AI-enabled chips. This includes everything from Edge devices to in-car applications, and even to data centres all of which must minimise thermal overheads. This will become increasingly important as products increasingly rely on AI at the Edge and less on cloud-based solutions.”

Embedded SRAM can be a significant power drain when, for example, pattern matching. Thus, on a large AI-enabled chip, memory can account for as much as 50% of the power usage and is thus a major contributor to power consumption and thermal load. The company estimates that using PowerMiser AI would reduce dynamic power consumption by up to 50% delivering compelling cuts in thermal load meaning heat sinks or other cooling systems are either not required or are dramatically reduced thereby increasing overall system reliability.

sureCore memory range

sureCore, as part of its bespoke custom memory development service, sureFIT, delivers memory sub-system solutions optimised for the three-dimensional design space of Power, Performance and Area (PPA). Whilst a bespoke solution offers the opportunity to engineer the optimal solution for the target application, sureCore has a range of power-optimised, standard products that deliver market-leading power profiles so urgently needed by these applications. These include Everon, PowerMiser, and MiniMiser. Further details can be found at on sureCore’s product page. Power savings can be realised both at nominal operating voltages and, increasingly importantly, at low to near threshold voltages allowing the application designers to tailor the power profile to the performance requirements. sureCore memories offer single rail, low voltage operation thereby allowing direct logic connection and significantly easing system level design considerations.