"IC designers have realized the benefits of proactive yield sensitivity analysis in deep sub-micron technologies," said Ken Liou, director of the IP and Design Support Division at UMC. "Ponte's Yield Analyzer provides Defect Limited Yield information which can be used by tools at virtually every step of the design flow starting from library/IP design and characterization to netlist generation, floorplanning, full chip detailed routing and ECO. Using Yield Analyzer, designers can use DD (Defect Density) data to analyze two or more layouts to evaluate and decide the best option for tape-out based on their requirements."
"We strongly believe that yield, traditionally the domain of fabs, must become a driving factor behind sub-90nm design flows," said Alex Alexanian, CEO of Ponte Solutions. "Ponte anticipated this trend more than two years ago and has worked with technology partners to develop and validate the accuracy, performance and usability of Yield Analyzer as design-stage yield characterization and analysis tool. Our partnership with UMC is an important milestone in bringing yield driven design methodologies to the design community."
About Ponte Solutions
Ponte Solutions, Inc., the design-for-yield company, manufactures and delivers unique, full-chip, model-based software products for semiconductor yield analysis and prediction, enabling designers to perform design-stage yield optimization. Ponte's customers include leading semiconductor manufacturers, foundries and design houses worldwide. Founded in 2002, the company has received funding from US Venture Partners, Telos Venture Partners, Incubic LLC, Silicom Ventures LLC and private individuals. The company has offices in Mountain View, California; Grenoble, France; Tokyo, Japan; and Yerevan, Armenia. More information about the company can be found at www.ponte.com
Ponte Solutions and Yield Analyzer are trademarks of Ponte Solutions, Inc. All other trademarks are properties of their respective owners.
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