The economic and environmental requirements for electronic circuits and systems to consume less power per function are going to endure with the electronic and EDA industries for the foreseeable future. Each year, advances must be made to continue this required trend in line with clear requirements specified in the International Technology Roadmap for Semiconductors (ITRS).
The Low Power Coalition (LPC) at Si2 is steadily making the required advances across the entire design flow; from Electronic System Level (ESL) all the way through implementation. Work is being done to define a complete power-aware reference flow that will be recommended to the industry. To aid in automating many of the steps along the tool chain, a tool-centric data model and associated Application Programming Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model. In addition, enhancements are being defined to extend the Common Power Format (CPF), an Si2 standard first released in March 2007.
This workshop will present the steps forward since the last Low Power Workshop at DAC 2007 and discuss future directions and end-user experiences with the technology developed and implemented so far. A selection of advanced tools that have been developed by some of the EDA companies will be presented to provide tangible progress in power-aware design. The topics and speakers include:
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1. Introduction to the Low Power Coalition |
| Gill Watt, Advanced Micro Devices - Chairman of the LPC |
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2. Low Power Design Format Requirements: Looking Ahead! |
| Bob Carver, Cadence Design Systems |
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3. LPC Low Power Reference Flow |
| David Hui, AMD, - Vice-Chair, Flow Working Group |
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4. LPC Data Model and API |
| David Hathaway, IBM, - Co-chair, Data Model and API WG |
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5. End-user Experiences |
| David Hui, AMD |
| Jake Buurma, Si2 |
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6. EDA Tool Developers for Low Power |
| Koorosh Nazifi, Cadence Design Systems |
| Jerry Frenkil, Sequence Design |
| Anmol Mathur, Calypto Design Systems |
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7. Panel Discussion (all presenters) |
| Other Si2-sponsored events at DAC include the 4th Integrated Design |
| Systems Workshop on June 9, from 12PM-4PM and the Si2 Member/Guest |
| Meeting on June 9, from 6PM-8PM. |
Links to more specific agendas and registration information can be found here: http://www.si2.org/?page=11
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVision Design Systems, Entasys, Freescale Semiconductor, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Logic (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). For further information on the Low Power Coalition, see http://www.si2.org/?page=726.
About Si2
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to-market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world.
Contact:
Silicon Integration Initiative, Austin
William Bayer, 512-342-2244,
ext. 304