Leading Semiconductor Companies Look to Dassault Systèmes to Improve Design Collaboration and Management
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Leading Semiconductor Companies Look to Dassault Systèmes to Improve Design Collaboration and Management

Gantry Group Survey Finds Dassault Systèmes ENOVIA Helps Companies Meet Industry Challenges by Managing Multi-Site Design, Improving Productivity and Maximizing IP Re-use

 

LOWELL, MA – November 12, 2008 – Dassault Systèmes (DS) (Euronext Paris: #13065, DSY.PA), a world leader in 3D and Product Lifecycle Management (PLM) solutions announced a new white paper from the Gantry Group which found that semiconductor companies using ENOVIA PLM solutions reported a number of clear benefits including a 74% increase in multi-site designs, a 46% savings in design engineering time and a 32% increase in product quality.

The study conducted by the Gantry Group, a technology research and ROI analysis company, entitled ROI Impact Analysis of ENOVIA Synchronicity DesignSync Data Manager, was based on a series of in-depth interviews with more than 15 of the top semiconductor companies who have deployed the ENOVIA Synchronicity DesignSync Data Manager solution.  

“In today’s economy, semiconductor companies cannot afford to waste time and money on an extensive, error-filled production process, nor can they afford to miss the small window they have to get new products out to market,” said Rick Stanton, Director, Global Semiconductor Strategy & Solutions ENOVIA R&D, Dassault Systèmes.  “The cost and timing pressures to ‘get it right the first time’ highlighted in the Gantry white paper demonstrate exactly why it is so important to have a strong collaboration and design management tool in place.”

ENOVIA Synchronicity DesignSync enables semiconductor companies to streamline business processes and reduce new product development time through one cohesive source of information that allows management and collaboration of design information, as well as visibility into the development process of each and every product.  Customers are able to improve engineering efficiency through implementing comprehensive IP Reuse and hierarchical, top-down design methodologies, decreasing costs, increasing first-sample success rate and reducing the design productivity gap.  For more information on ENOVIA Synchronicity DesignSync and other ENOVIA solutions for the semiconductor industry, please visit the company’s Web site.

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