[ Chapter start ] [ Previous page ] [ Next page ] B.4 Verilog HDL LRMAn important feature of Verilog is the ability to extend tools by writing your own code and integrating it with a Verilog-based tool. For example, the following code calls a user-written system task, : Here is the C program, hello.c , that prints the full hierarchical name of the instance in which the Verilog code containing the call to is located: { handle mod_handle; char *full_name; acc_initialize(); mod_handle = acc_handle_tfarg(1); io_printf("Hello from: %s ", acc_fetch_fullname(mod_handle)); The details of how to compile and link your program with the Verilog executable depend on the particular tool; the names, functions, and parameters of ACC routines, the header files, veriuser.h and acc_user.h (most companies include these with their Verilog products), as well as older TF routines and the newer VPI routines are described in detail in Sections 17–23 of the 95 LRM. Annex F of the 95 LRM describes widely used Verilog system tasks and functions that are not required to be supported as part of IEEE Std 1364-1995. Table B.3 summarizes these tasks and functions. Annex G of the 95 LRM describes additional compiler directives that are not part of IEEE Std 1364-1995 and are not often used by ASIC designers. Two directives, `default_decay_time and `default_trireg_strength , are used to model charge decay and the strength of high-impedance trireg nets. Four more compiler directives: `delay_mode_distributed , `delay_mode_path , `delay_mode_unit, and `delay_mode_zero are used to specify the delay mode for modules. [ Chapter start ] [ Previous page ] [ Next page ] |
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