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5.4.1 Logic Expanders

The basic logic cell for the Altera MAX architecture, a macrocell, is a descendant of the PAL. Using the logic expander , shown in Figure 5.13 to generate extra logic terms, it is possible to implement functions that require more product terms than are available in a simple PAL macrocell. As an example, consider the following function:

F = A' · C · D + B' · C · D + A · B + B · C'.(5.22)

This function has four product terms and thus we cannot implement F using a macrocell that has only a three-wide OR array (such as the one shown in Figure 5.13 ). If we rewrite F as a “sum of (products of products)” like this:

F = (A' + B') · C · D + (A + C') · B

= (A · B)' (C · D) + (A' · C)' · B ;(5.23)

we can use logic expanders to form the expander terms (A · B)' and (A' · C)' (see Figure 5.13 ). We can even share these extra product terms with other macrocells if we need to. We call the extra logic gates that form these shareable product terms a shared logic expander , or just shared expander .

The disadvantage of the shared expanders is the extra logic delay incurred because of the second pass that you need to take through the product-term array. We usually do not know before the logic tools assign logic to macrocells ( logic assignment ) whether we need to use the logic expanders. Since we cannot predict the exact timing the Altera MAX architecture is not strictly deterministic . However, once we do know whether a signal has to go through the array once or twice, we can simply and accurately predict the delay. This is a very important and useful feature of the Altera MAX architecture.

The expander terms are sometimes called helper terms when you use a PAL. If you use helper terms in a 22V10, for example, you have to go out to the chip I/O pad and then back into the programmable array again, using two-pass logic .

Another common feature in complex PLDs, also used in some PLDs, is shown in Figure 5.13 . Programming one input of the XOR gate at the macrocell output allows you to choose whether or not to invert the output (a '1' for inversion or to a '0' for no inversion). This programmable inversion can reduce the required number of product terms by using a de Morgan equivalent representation instead of a conventional sum-of-products form, as shown in Figure 5.14 .

As an example of using programmable inversion, consider the function

F = A · B' + A · C' + A · D' + A' · C · D ,(5.24)

which requires four product terms—one too many for a three-wide OR array.

If we generate the complement of F instead,

F ' = A · B · C · D + A' · D' + A' · C' ,(5.25)

this has only three product terms. To create F we invert F ', using programmable inversion.

Figure 5.15 shows an Altera MAX macrocell and illustrates the architectures of several different product families. The implementation details vary among the families, but the basic features: wide programmable-AND array, narrow fixed-OR array, logic expanders, and programmable inversion—are very similar. ¹ Each family has the following individual characteristics:

• A typical MAX 5000 chip has: 8 dedicated inputs (with both true and complement forms); 24 inputs from the chipwide interconnect (true and complement); and either 32 or 64 shared expander terms (single polarity). The MAX 5000 LAB looks like a 32V16 PLD (ignoring the expander terms).
• The MAX 7000 LAB has 36 inputs from the chipwide interconnect and 16 shared expander terms; the MAX 7000 LAB looks like a 36V16 PLD.
• The MAX 9000 LAB has 33 inputs from the chipwide interconnect and 16 local feedback inputs (as well as 16 shared expander terms); the MAX 9000 LAB looks like a 49V16 PLD.

FIGURE 5.15  The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array Block). (c) A MAX family macrocell. The macrocell details vary between the MAX families—the functions shown here are closest to those of the MAX 9000 family macrocells.

FIGURE 5.16  The timing model for the Altera MAX architecture. (a)  A direct path through the logic array and a register. (b) Timing for the direct path. (c) Using a parallel expander. (d) Parallel expander timing. (e) Making two passes through the logic array to use a shared expander. (f) Timing for the shared expander (there is no register in this path). All timing values are in nanoseconds for the MAX 9000 series, '15' speed grade. ( Source: Altera.)

5.4.2 Timing Model

Figure 5.16 shows the Altera MAX timing model for local signals. ² For example, in Figure 5.16 (a) an internal signal, I1, enters the local array (the LAB interconnect with a fixed delay t ₁ = t _LOCAL = 0.5 ns), passes through the AND array (delay t ₂ = t _LAD = 4.0 ns), and to the macrocell flip-flop (with setup time, t ₃ = t _SU = 3.0 ns, and clock–Q or register delay , t ₄ = t _RD = 1.0 ns). The path delay is thus: 0.5 + 4 +3 + 1 = 8.5 ns.

Figure 5.16 (c) illustrates the use of a parallel logic expander . This is different from the case of the shared expander ( Figure 5.13 ), which required two passes in series through the product-term array. Using a parallel logic expander, the extra product term is generated in an adjacent macrocell in parallel with other product terms (not in series—as in a shared expander).

We can illustrate the difference between a parallel expander and a shared expander using an example function that we have used before (Eq.  5.22 ),

F = A' · C · D + B' · C · D + A · B + B · C' .(5.26)

This time we shall use macrocell M1 in Figure 5.16 (d) to implement F1 equal to the sum of the first three product terms in Eq.  5.26 . We use F1 (using the parallel expander connection between adjacent macrocells shown in Figure 5.15 ) as an input to macrocell M2. Now we can form F = F1 + B · C' without using more than three inputs of an OR gate (the MAX 5000 has a three-wide OR array in the macrocell, the MAX 9000, as shown in Figure 5.15 , is capable of handling five product terms in one macrocell—but the principle is the same). The total delay is the same as before, except that we add the delay of a parallel expander, t _PEXP = 1.0 ns. Total delay is then 8.5 + 1 = 9.5 ns.

Figure 5.16 (e) and (f) shows the use of a shared expander—similar to Figure 5.13 .

The Altera MAX macrocell is more like a PLD than the other FPGA architectures discussed here; that is why Altera calls the MAX architecture a complex PLD. This means that the MAX architecture works well in applications for which PLDs are most useful: simple, fast logic with many inputs or variables.

5.4.3 Power Dissipation in Complex PLDs

A programmable-AND array in any PLD built using EPROM or EEPROM transistors uses a passive pull-up (a resistor or current source), and these macrocells consume static power . Altera uses a switch called the Turbo Bit to control the current in the programmable-AND array in each macrocell. For the MAX 7000, static current varies between 1.4 mA and 2.2 mA per macrocell in high-power mode (the current depends on the part—generally, but not always, the larger 7000 parts have lower operating currents) and between 0.6 mA and 0.8 mA in low-power mode. For the MAX 9000, the static current is 0.6 mA per macrocell in high-current mode and 0.3 mA in low-power mode, independent of the part size. ³ Since there are 16 macrocells in a LAB and up to 35 LABs on the largest MAX 9000 chip (16 ¥ 35 = 560 macrocells), just the static power dissipation in low-power mode can be substantial (560 ¥ 0.3 mA ¥ 5 V = 840 mW). If all the macrocells are in high-power mode, the static power will double. This is the price you pay for having an (up to) 114-wide AND gate delay of a few nanoseconds (t _LAD = 4.0 ns) in the MAX 9000. For any MAX 9000 macrocell in the low-power mode it is necessary to add a delay of between 15 ns and 20 ns to any signal path through the local interconnect and logic array (including t _LAD and t _PEXP ).