7.3  Xilinx EPLD

The Xilinx EPLD family uses an interconnect bus known as Universal Interconnection Module ( UIM ) to distribute signals within the FPGA. The UIM, shown in Figure 7.7 , is a programmable AND array with constant delay from any input to any output. In Figure 7.7 :

• C _G is the fixed gate capacitance of the EPROM device.
• C _D is the fixed drain parasitic capacitance of the EPROM device.
• C _B is the variable horizontal bus (“bit” line) capacitance.
• C _W is the variable vertical bus (“word” line) capacitance.

Figure 7.7 shows the UIM has 21 output connections to each FB. 1 Thus the XC7272 UIM (with a 4 ¥ 2 array of eight FBs as shown in Figure 7.7 ) has 168 (8 ¥ 21) output connections. Most (but not all) of the nine I/O cells attached to each FB have two input connections to the UIM, one from a chip input and one feedback from the macrocell output. For example, the XC7272 has 18 I/O cells that are outputs only and thus have only one connection to the UIM, so n = (18 ¥ 8) – 18 = 126 input connections. Now we can calculate the number of tracks in the UIM: the XC7272, for example, has H = 126 tracks and V = 168/2 = 84 tracks. The actual physical height, V , of the UIM is determined by the size of the FBs, and is close to the die height.

The UIM ranges in size with the number of FBs. For the smallest XC7236 (with a 2 ¥ 2 array of four FBs), the UIM has n = 68 inputs and 84 outputs. For the XC73108 (with a 6 ¥ 2 array of 12 FBs), the UIM has n = 198 inputs. The UIM is a large array with large parasitic capacitance; it employs a highly optimized structure that uses EPROM devices and a sense amplifier at each output. The signal swing on the UIM uses less than the full V _DD = 5 V to reduce the interconnect delay.

[ Chapter start ] [ Previous page ] [ Next page ]