"Mentor's verification vision is to deliver an environment where the verification process is completely abstracted from the underlying verification engines from first design thoughts, through silicon, to final product," said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. "With EVP, Mentor has eliminated the barriers to hardware acceleration and ushered in a new era of enterprise-level verification that combines the functionality and observability of simulation-based verification with the speed of emulation."
Veloce OS3 and Mentor VIP Transform Emulation into a Global, High-Performance Datacenter Resource
To leverage the investment in emulation and allow it to serve as a true enterprise verification resource, emulation must undergo a transformation from project-bound engineering lab instrument to datacenter-hosted global resource. This transformation begins by eliminating the In-Circuit Emulation (ICE) tangle of cables, speed adaptors and physical devices, replacing them with virtual devices. The Veloce OS3 VirtuaLAB peripherals are reconfigured instantly to support multiple projects and rapidly shifting priorities. This is possible because VirtuaLAB is hosted on standard datacenter computers, not proprietary hardware targets.
The OS3 Enterprise Server efficiently manages the global emulation resources, consolidating them to commercial queue managers as a single, high-capacity entity. The Enterprise Server determines the most efficient location to run each job and immediately serves high-priority jobs by temporarily suspending jobs of lower priority.
Veloce OS3 also delivers advanced verification features to the emulator including PSL/SystemVerilog assertions, functional coverage, and UPF for low power. This enables a high-performance coverage closure flow and pre-silicon performance analysis of critical SoC subsystems running application software. To maximize testbench reuse, the Mentor Verification IP, built using standard UVM/RTL, is designed for both simulation and acceleration modes. These capabilities are in place for a smooth transition from simulation to emulation, allowing for a 1000X performance boost over simulation alone with no loss of functionality.
New Visualizer Debugger and Software Debug Suite
With System on Chip (SoC) designs, teams are spending the largest percentage of their verification time on debug, so improving debug productivity from block to system is critical. The new Visualizer debugger is a single debug solution tightly integrated into simulation and emulation that has the capacity and performance to handle today's largest SoCs. The Visualizer debugger provides efficient RTL; gate-level and testbench debug, including automatic tracing to quickly pinpoint original cause of errors; protocol and transaction-level debugging; a complete set of native UVM and SystemVerilog class-based debugging capabilities and low-power UPF debug. All of these capabilities are available in both interactive and post-simulation modes for simulation and emulation.
SoC signoff is not complete until the ability to boot the OS has been verified. SW debug of the OS has a large think-time component while the emulator sits idle. OS3 moves the think-time offline to the Codelink® tool, which supports 10X the number of engineers as single-user JTAG probes and replays SW execution at speeds of up to 100Mhz. With OS3, the emulator attacks job after job at full speed while SW debug is performed offline. Together these capabilities enable maximum debug productivity and OS bring-up much earlier in the design cycle.
Unified Coverage and Analysis Boost Quality and Productivity of Results and Optimizes Emulator Requirements for Coverage Logic
Many SoC projects have verification data coming from multiple sources that must be intelligently merged and holistically analyzed to evaluate true project completeness. With Veloce OS3 and Questa 10.3, assertions, coverage and runtime data from all sources — including emulation, formal, simulation, mixed-signal and low power — are written into the high-performance database. Using a common database and Questa Verification Management tools and testplans, verification teams can instantly view coverage, pinpoint ineffective tests, reduce data merge times and improve regression throughput and debug time, collectively resulting in enhanced quality of results and productivity.
The EVP Unified Coverage Database (UCDB), which supports the Unified Coverage Interoperability Standard (UCIS), is also used to create a "smarter" coverage closure flow with emulation by understanding coverage that has already been met by other verification engines and intelligently optimizing the coverage logic that is downloaded into the emulator; saving compile time and valuable emulation resources.
Availability
The Mentor Enterprise Verification Platform components are scheduled for general availability in late Q2 2014.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:
http://www.mentor.com/.
Mentor Graphics, Mentor, Questa, Veloce and Codelink are registered trademarks and Visualizer is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
For more information, please contact:
Carole Dunn
Mentor Graphics
503.685.4716
Email Contact
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SOURCE Mentor Graphics Corporation
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