Synopsys' Digital, Signoff, Custom Implementation and AMS Tools Ready for Early 12-nm Production Designs

Highlights:

• 12-nm physical implementation flow is fully enabled in IC Compiler II place-and-route and IC Validator physical signoff
• Joint development of innovative new area-optimization technologies, including  new standard cell structures support by IC Compiler II
• Custom Compiler is ready to use with TSMC's 12-nm process, with immediate availability of the Process Design Kits (PDKs)

Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified the complete suite of products in the Synopsys Galaxy™ Design Platform for the most current version of 12-nanometer (nm) FinFET process technology. This 12-nm certification brings with it the broad body of design collateral, including routing rules, physical verification runsets, signoff-accurate extraction technology files, SPICE correlated timing and interoperable process design kits (iPDKs) for this latest FinFET process. Synopsys Custom Compiler™ design solution support is enabled through an iPDK.

To accelerate access to this power-efficient, high-density process, IC Compiler™ II place-and-route system has been enabled to support new standard cell architectures seamlessly co-existing with 16FFC intellectual property (IP). Recent collaborations have resulted in enhancements to IC Compiler II's core placement and legalization engines ensuring maximum utilization while minimizing placement fragmentation and cell displacement. The 12-nm ready iPDK enables designers to use Custom Compiler's layout assistant features to shorten time in creating FinFET layouts.

"This power-efficient, high-density node offers a broad set of opportunities to our customers, enabling them to deliver highly differentiated products," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Our ongoing collaboration with Synopsys is helping expedite designer access to 12-nm process technology."

"The long-standing collaboration between Synopsys and TSMC continues to be key in bringing accelerated access to new process technology nodes," said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. "With the Galaxy Design Platform certified for 12-nm readiness, our mutual customers are enabled to speed up development and deployment to accelerate their time-to-market."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
Carole Murchison
Synopsys, Inc.
650-584-4632
Email Contact

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SOURCE Synopsys, Inc.