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[ Chapter start ] [ Previous page ] [ Next page ] 15.6 FPGA PartitioningIn Section 15.3 we saw how many different issues have to be considered when partitioning a complex system into custom ASICs. There are no commercial tools that can help us with all of these issues—a spreadsheet is the best tool in this case. Things are a little easier if we limit ourselves to partitioning a group of logic cells into FPGAs—and restrict the FPGAs to be all of the same type. 15.6.1 ATM SimulatorIn this section we shall examine a hardware simulator for Asynchronous Transfer Mode ( ATM ). ATM is a signaling protocol for many different types of traffic including constant bit rates (voice signals) as well as variable bit rates (compressed video). The ATM Connection Simulator is a card that is connected to a computer. Under computer control the card monitors and corrupts the ATM signals to simulate the effects of real networks. An example would be to test different video compression algorithms. Compressed video is very bursty (brief periods of very high activity), has very strict delay constraints, and is susceptible to errors. ATM is based on ATM cells (packets). Each ATM cell has 53 bytes: a 5-byte header and a 48-byte payload; Figure 15.4 shows the format of the ATM packet. The ATM Connection Simulator looks at the entire header as an address.
Figure 15.5 shows the system block diagram of the ATM simulator designed by Craig Fujikami at the University of Hawaii. Now produced by AdTech, the simulator emulates the characteristics of a single connection in an ATM network and models ATM traffic policing, ATM cell delays, and ATM cell errors. The simulator is partitioned into the three major blocks, shown in Figure 15.5 , and connected to an IBM-compatible PC through an Intel 80186 controller board together with an interface board. These three blocks are
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